Arteris Press Releases

Faster time-to-market and on-chip data protection enable rapid innovation

CAMPBELL, Calif. — March 30, 2017 — Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced that Ethertone Technologies has licensed Arteris FlexNoC interconnect IP for use in enterprise storage controllers and networking processors.

Our development team chose Arteris FlexNoC interconnect IP because of its ease-of-use and on-chip data protection features.

Tao Zhong, VP of IC Design, Ethertone Technologies

Best-in-class interconnect IP allows for easier creation of turnkey solutions

CAMPBELL, Calif. — March 22, 2017 — Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced that Samsung Electronics has licensed Arteris FlexNoC interconnect IP for use by its foundry customers.

Leading Chinese systems manufacturer purchases multiple licenses for cache coherent interconnect IP and network-on-chip fabric IP

CAMPBELL, Calif. — March 14, 2017 — Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced that the chip design division of ZTE has licensed the highly-configurable Arteris^® Ncore™ cache coherent interconnect IP as well as the Arteris FlexNoC® interconnect IP for use in its advanced systems-on-chip (SoC).

We chose Arteris Ncore interconnect IP and Arteris FlexNoC IP after an extensive evaluation where we ascertained technology to address the optimal mixing of ARM- and PCIe-based traffic in complex embedded systems.

Mr. Yu Li, Vice President, ZTE

CAMPBELL, Calif. — March 8, 2017 — Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced its next generation automated interconnect timing solution – the PIANO 2.0 Timing Closure Package. PIANO 2.0 builds on customer silicon experience gathered with FlexNoC Physical^™ package to automate interconnect timing closure for both cache coherent and non-coherent subsystems.

By applying PIANO 2.0 together with generated placement guides, Renesas was able to close the complex SoC development sooner than we expected. Renesas has been an early user of Arteris’ closure technology, and we plan to continue to use Arteris’ enhanced closure capabilities for our future SoC developments.

Horst Rieger, Manager, Design Services, European Technology Center, Renesas Electronics Europe