Technology increases area and power efficiency of systems built with semiconductor IP from multiple sources
CAMPBELL, California — May 17, 2016 — Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today introduced a semiconductor design technology that enhances the ability of SoC architects to create efficient cache-coherent systems with IP sourced from multiple vendors. Allowing the industry’s first distributed heterogeneous cache-coherent interconnect, the new technology helps designers achieve higher frequency, lower power consumption and reduced time-to-market in producing differentiated SoCs that span multiple design domains such as mobility, HDTV, enterprise storage, automotive advanced driver assistance systems (ADAS), micro-server and networking markets.
The exploding cost of the latest semiconductor process nodes is forcing design teams to evaluate new architectural approaches for SoC design. The distributed cache coherent architecture that Arteris offers will help system designers better utilize the processing resources in the SoC, making computing throughput more efficient.
Linley Gwennap, Principal Analyst, The Linley Group
The Arteris design team has created an architecture that allows designers to configure a cache coherent interconnect with multiple fully-coherent agent ports in a protocol-agnostic manner, providing far greater configurability than fixed and centralized cache coherency interconnects typically found in today’s SoCs. Additionally, the Arteris technology increases the performance of non-coherent agents that access the coherent subsystem using proxy cache technology (also called “I/O cache”), providing the capability for non-coherent IP to achieve the benefits of system-wide coherency.
The technology is highly configurable and allows SoC architects to select the number of coherent agents and memory interface ports, numbers and sizes of configurable snoop filters, and number and sizes of proxy caches and “victim” last-level caches. This distributed hardware architecture eases physical implementation and timing closure because it is more naturally aligned with physical floor plan constraints.
It supports heterogeneous cache coherent systems by concurrently enabling different coherent protocol implementations, cache state models and cache organizations. These features give designers the greatest degree of configurability available in the industry, benefiting SoC frequency, latency and power consumption for the unique needs of each system.
- Heterogeneous Coherent Agents - Allows smooth interoperability of different coherent protocol implementations, cache state models and cache organizations, enabling use of coherent IP from multiple vendors and internal development teams.
- Distributed Architecture – Eases floor planning and timing closure while enabling flexible clock and power management.
- Multiple Configurable Snoop Filters – Configure the organization, size and associativity of multiple individual snoop filters based on caching agent characteristics in the system, reducing the overall memory footprint required for the system.
- Proxy Caches – Enable non-coherent IP to achieve the benefits of system-wide coherency.
- Scalability – Architecture consists of replicated components with a configurable number of ports per component, allowing the interconnect IP to scale to fit a variety of processing requirements.
“Current interconnect technology is inadequate for addressing the level of complexity that today’s advanced SoCs require,” said K. Charles Janac, President and CEO of Arteris. “We’ve developed a new architecture specifically to provide system architects with the flexibility and configurability required to meet application-specific performance goals for the most demanding systems. Our technology provides core system features not available anywhere else.”
The Linley Group: “The exploding cost of the latest semiconductor process nodes is forcing design teams to evaluate new architectural approaches for SoC design,” said Linley Gwennap, principal analyst of The Linley Group. “The distributed cache coherent architecture that Arteris offers will help system designers better utilize the processing resources in the SoC, making computing throughput more efficient. This technology will also simplify timing closure because it is more friendly to industry-standard synthesis-place-and-route tools.”
Heterogeneous System Architecture (HSA) Foundation: “One of the key goals of the Heterogeneous System Architecture (HSA) Foundation is to encourage efforts that allow processing elements beyond CPUs and GPUs to participate as equal citizens in a shared virtual memory environment,” said Greg Stoner, chairman of the HSA Foundation. “The Arteris cache coherent interconnect technology offers engineers a way to achieve this goal in a practical fashion. This approach is aligned with the objectives outlined in the HSA Platform System Architecture Specification 1.0 and is a welcome development for the industry.”
Arteris, Inc. provides system-on-chip (SoC) interconnect IP and tools to accelerate SoC semiconductor assembly for a wide range of applications. Rapid semiconductor designer adoption by customers such as Samsung, Huawei / Hisilicon, Mobileye, Altera, and Texas Instruments has resulted in Arteris being the only semiconductor IP company to be ranked in the Inc. 500 and Deloitte Technology Fast 500 lists in 2012 and 2013. Customer results obtained by using the Arteris product line include lower power, higher performance, more efficient design reuse and faster SoC development, leading to lower development and production costs. More information can be found at www.arteris.com.
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