Independent White Paper Describes Die Size, Power Consumption, Project Design Time and Performance Benefits of NoC Technology
SUNNYVALE, California – May 04, 2011 – Network on chip interconnect IP such as that pioneered by Arteris can more than pay for itself in the first SoC design, according to a new white paper released today by Objective Analysis, a semiconductor market research firm. The white paper titled "NoC Interconnect Improves SoC Economics" points out that companies that adopted NoC interconnect IP reaped performance and cost benefits that more than offset their initial investment in the IP.
Readers can download the white paper here.
“In every case that we examined we found that the economic benefits of smaller die size, shorter development cycles, and faster time to market more than offset the licensing cost of the technology, essentially allowing NoC technology to pay for itself in the first design.”
Jim Handy, Director, Objective Analysis
“In researching system on chip assembly and IP integration, we found that a network on chip interconnect approach allows design teams to build faster and better chips much more quickly than they could using conventional bus and crossbar interconnect fabrics,” said Jim Handy, Director of Objective Analysis. “In every case that we examined we found that the economic benefits of smaller die size, shorter development cycles, and faster time to market more than offset the licensing cost of the technology, essentially allowing NoC technology to pay for itself in the first design.”
Objective Analysis assessed data from four companies doing complex integrated circuit design. On average, their SoCs were comprised of 55 IP blocks, and the time and effort required to develop an interconnect strategy to connect them was considered one of the biggest challenges to meet demanding market requirements by design teams.
The inventor and leading supplier of network-on-chip (NoC) interconnect IP solutions is Arteris Inc., based in Silicon Valley and Paris, France. Arteris’ FlexNoC interconnect IP products reduce routing congestion, ease timing closure, and enable fast IP swapping for the easy creation of SoC derivatives and quick response to engineering change orders (ECOs). In March, Arteris announced it was cash flow positive and profitable on an accounting basis for Q4 2010 due to significantly increased adoption of its FlexNoC network on chip interconnect IP products by major semiconductor manufacturer customers.
“The research by Objective Analysis quantifies the economic benefits of using NoC interconnect technology in today's SoCs,” said K. Charles Janac, President and CEO of Arteris. “The ability of our network on chip technology to reduce wire routing congestion, ease timing closure, and facilitate quick IP block changes for SoC derivatives or late engineering change orders provides significant cost and revenue benefits over traditional bus and crossbar technologies.”
Arteris, Inc. provides Network-on-Chip interconnect IP and tools to accelerate System-on-Chip semiconductor (SoC) assembly for a wide range of applications. Results obtained by using the Arteris product line include lower power, higher performance, more efficient design reuse and faster development of ICs, SoCs and FPGAs.
Founded by networking experts and offering the first commercially available Network-on-Chip IP products, Arteris operates globally with headquarters in San Jose, California and an engineering center in Paris, France. Arteris is a private company backed by a group of international investors including ARM Holdings, Crescendo Ventures, DoCoMo Capital, Qualcomm Incorporated, Synopsys, TVM Capital, and Ventech. More information can be found at www.arteris.com.
About Objective Analysis
Objective Analysis (www.Objective-Analysis.com) offers third-party independent market research and data for the semiconductor industry and investors in the semiconductor industry.
Arteris, FlexNoC and the Arteris logo are trademarks of Arteris. All other product or service names are the property of their respective owners.
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