Release 11.0 from foundry leader addresses interconnect fabric for the first time;
Includes support for Arteris on-chip interconnect IP and tools
SAN JOSE, California – June 22, 2010– Arteris Inc., the leading interconnect IP solutions provider, today announced that its Network–on-Chip (NoC) interconnect IP and tools will be available to TSMC customers as part of TSMC Reference Flow 11.0, the foundry’s latest design reference flow for its advanced process technology. The TSMC support for Arteris Network-on-Chip (NoC) interconnect IP is a milestone where a silicon foundry has incorporated an interconnect IP solution into a reference flow, providing designers with an efficient way to manage the complexity and performance of highly integrated SoCs. Arteris ships a commercial NoC IP solution and its NoC-connected SoCs are incorporated in commercially available systems, such as LCD projectors and Digital Televisions.
Since 2006, Arteris has refined its set of tools and IP, working with leading SoC makers worldwide, to provide an integrated, flexible, and production-proven approach to implementing an efficient on-chip communications system within complex SoC designs. Its technology, which is available as licensable IP and a suite of intuitive design tools compatible with existing EDA flows, is used by designers to manage on-chip communications of top-level SoC interconnect, sub-systems, IP blocks, and other elements on a chip. The Arteris FlexNoC™ solution significantly reduces the time and complexity of developing today’s highly integrated SoCs while improving power, performance, and area.
“TSMC has set the standard for advanced design methodologies with each release of its reference flow, and Release 11.0 takes design efficiency to a new level with the support of essential design requirements such as on-chip interconnect. Arteris’s NoC interconnect IP and tools provide a key enhancement to design methodologies through increased automation and architectural innovation to ensure customers a smooth path to silicon,” said Charlie Janac, Arteris President and CEO. “We are pleased to be the provider of NoC technology to support TSMC design flow and to be part of TSMC’s very forward-thinking Open Innovation Platform. We look forward to working with mutual customers to help implement leading-edge SoC solutions optimized for TSMC’s manufacturing processes.”
“Release 11.0 continues TSMC’s progress toward providing a reference flow and design methodology that supports design at higher levels of abstraction and includes more innovative approaches to solving the toughest challenges our customers face. A number of these challenges, such as routing congestion and timing closure, can best be solved at the architectural level,” said ST Juang, Senior Director, Design Infrastructure Marketing Division. “Having an on-chip interconnect strategy is an increasingly critical aspect of advanced IC design. The support of their NoC IP solution in Release 11.0 will offer our customers a path for improving the efficiency of how they manage the complexity of their designs.”
Arteris, Inc. provides semiconductor interconnect IP, and tools to improve communication performance of ICs for wide range of applications. Results obtained by using Arteris's IP product line include lower power, higher performance, lower risk of development and faster delivery of simple to complex ICs, SoCs and FPGAs.
Founded by networking experts, Arteris operates globally with headquarters in San Jose, California and an engineering center in Paris, France. Arteris is a private company backed by a group of international investors including ARM Holdings, Crescendo Ventures, DoCoMo Capital, Qualcomm Incorporated, Synopsys, TVM Capital, and Ventech. More information can be found at www.arteris.com.
Arteris and the Arteris logo are trademarks of Arteris, Inc.
Open Innovation Platform is a trademark of Taiwan Semiconductor Manufacturing Company, Ltd.