Enables next-generation machine learning and autonomous driving SoCs with support for Arm AMBA CHI protocol, CCIX, and ISO 26262 Functional Safety
Linley Processor Conference 2017, SANTA CLARA, Calif. — October 4, 2017 — ArterisIP, the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced the Ncore Cache Coherent Interconnect IP version 3 along with the optional Ncore Resilience Package for functional safety.
As current users of the Ncore cache coherent interconnect, we are excited about the technical innovation in ArterisIP’s new Ncore 3 IP. Enabling both the AMBA CHI and ACE protocols in the same SoC will allow for greater use of existing IP in high-performance systems.
Mr. Yu Li, Vice President , ZTE (SaneChips)