Arteris Press Releases

Long-time FlexNoC interconnect user implements hardware-based functional safety technologies for ISO 26262 qualification of autonomous vehicles

CAMPBELL, Calif. — Sep. 27, 2016 — Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced that Mobileye, the global pioneer and leader in camera-based Advanced Driver Assistance Systems (ADAS), has licensed Arteris FlexNoC interconnect IP, as well as FlexNoC Physical and FlexNoC Resilience Packages for use in its next-generation EyeQ5® vision-based SoC family.

For years, Arteris technology has allowed us to continually increase the performance of each EyeQ ADAS SoC generation while reducing wire routing congestion and timing closure issues. The data protection technologies in the FlexNoC Resilience Package allow us to more easily implement state-of-the-art functional safety features in hardware, which simplifies the tasks of our software development teams as we strive to meet the most stringent ISO 26262 requirements.

Elchanan Rushinek, Vice President of Engineering, Mobileye

Physically aware network-on-chip IP reduces timing closure effort and time-to-market

CAMPBELL, Calif. – Jan. 5, 2016 – Arteris Inc., the inventor and leading supplier of silicon-proven commercial Network-on-Chip (NoC) interconnect IP solutions, today announced that Renesas Electronics Europe has licensed Arteris^® FlexNoC Physical™ IP for use in its High-End SoC business division.

New version improves SoC designer productivity, provides foundation for future technologies

CAMPBELL, California — April 22, 2015 — Arteris Inc., the inventor and only supplier of silicon-proven commercial network-on-chip (NoC) interconnect IP solutions,  today announced availability of Arteris FlexNoC Physical interconnect IP, a breakthrough that accelerates system-on-chip (SoC) physical design.

Arteris is solving an important set of back-end problems with technology that works earlier in the SoC design flow. FlexNoC Physical IP has the potential to significantly decrease timing issues experienced in the layout stage, reducing P&R iterations and engineering change orders (ECOs) and saving cost and schedule time.

Mike Demler, Senior Analyst, The Linley Group

Arteris FlexNoC Physical has the promise to improve layout productivity by providing Synopsys tools, such as Design Compiler Graphical and IC Compiler II, with improved timing closure information and more accurate RTL data. We look forward to working with mutual customers to validate these propositions.

Bijan Kiani, Vice President of Marketing, Design Group, Synopsys