Arteris Press Releases

Sondrel Deploys Arteris IP for Next-Generation Multi-Channel Automotive SoC

Configurability and Performance of FlexNoC is Key to Design of High-Performance Compute IP Platform for ADAS Applications

READING, UK and CAMPBELL, Calif. – May 3, 2022 -- Sondrel and Arteris IP (Nasdaq: AIP), a leading provider of system IP consisting of network-on-chip (NoC) interconnect and IP deployment software that accelerate system-on-chip (SoC) creation, today announced that Sondrel is adopting FlexNoC interconnect IP in its next generation of advanced driver-assistance systems (ADAS) architecture. The onchip-interconnect was selected for its configurability and performance. The product enables the SFA 350A multi-channel automotive vehicle IP platform requirements. FlexNoC supports the ability to design the NoC to match the performance of IP blocks to ensure that data flows at the right speed in, out and around the SoC. It enables designers to quickly design and verify a chip that precisely meets the customer’s silicon specifications on time and within budget.

 

Through many years of working with Arteris, we knew that FlexNoc would reliably deliver exactly what we needed, backed up by excellent technical support. The SoC interconnect provides a complete, comprehensive solution spanning architecture exploration to physical implementation and verification."


Edwin Loverseed, Head of Engineering, Sondrel

 

Topics: IP System-on-Chip NoC ISO 26262 Networks-On-Chip Arteris FlexNoC automotive ADAS radar soc architecture verification LIDAR SoCs high-performance sensors ASIC ip deployment Arteris IP (AIP) SFA 350A processor silicon chips compute solutions Edwin Loverseed

Arteris IP's Stefano Lorenzini to Speak at Automotive IQ Application of ISO 26262 Berlin Conference

CAMPBELL, Calif. – April 25, 2022 – Arteris IP (NASDAQ: AIP), a leading provider of system IP consisting of network-on-chip (NoC) interconnect and IP deployment software that accelerate system-on-chip (SoC) creation, today announced that Functional Safety Manager Stefano Lorenzini will present at the Automotive IQ Application of ISO 26262 Conference on Wednesday, April 27, 2022, at Hilton Berlin, Germany. His keynote presentation, Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip, begins at 11:15 (CEST).

Topics: SoC System-on-Chip NoC functional safety ISO 26262 SoC design Networks-On-Chip soc architecture arteris ip functional safety manager FMEDA IEC 61508 ip deployment Stefano Lorenzini AIP Berlin Conference Automotive IQ

Arteris® IP FlexNoC® Interconnect and Resilience Package Licensed in Neural Network Accelerator Chip Project Led by BMW Group

NoC interconnect IP to be dataflow backbone of German Federal Ministry of Education and Research (BMBF) project chip to advance automotive artificial intelligence and machine learning (AI/ML) processing.

CAMPBELL, Calif. – April 5, 2022 – Arteris IP (NASDAQ: AIP), a leading provider of system-on-chip (SoC) system IP consisting of network-on-chip (NoC) interconnect and IP deployment software that accelerate SoC creation, today announced that BMW Group has licensed FlexNoC interconnect IP and the accompanying FlexNoC Resilience Package IP for use in a chip partially funded by the German Federal Ministry of Education and Research (BMBF) as part of the ZUSE-KI-mobil publicly funded project. The goal of the project is to develop an accelerator chip for high-end deep learning applications that is a leap forward in terms of energy efficiency, reliability, robustness and security, which go far beyond current possibilities. BMW Group is serving as the coordinator and leader of the project.

We are excited that the consortium led by BMW Group chose Arteris IP interconnect technology as the on-chip communications on-chip network for this innovative automotive system-on-chip. BMW Group’s decision to use our interconnect IP as the dataflow on-chip network of this complex system is a testimony to the benefits our technologies bring to design teams creating the world’s most sophisticated AI/ML processing chips."


K. Charles Janac, President and CEO, Arteris IP

Topics: System-on-Chip functional safety Arteris FlexNoC automotive flexnoc resilience package reliability machine learning artificial intelligence neural network AI latency SoCs power efficiency noc interconnect on-chip communications dataflow Arteris IP FlexNoC interconnect AI/ML ip deployment mobile usage IP blocks system ip Arteris IP (AIP) BMW Group ZUSE-KI-mobil processing chips BMBF

Arteris IP Announces Filing of Registration Statement for Proposal Initial Public Offering

CAMPBELL, Calif. – October 4, 2021 – Arteris IP, a leading provider of system-on-chip (SoC) system intellectual property ("IP") consisting of network-on-chip (NoC) interconnect IP and IP deployment software, today announced it has publicly filed a registration statement on Form S-1 with the U.S. Securities and Exchange Commission ("SEC") relating to a proposed initial public offering of its common stock. The number of shares to be offered and the price range for the proposed offering have not yet been determined. Arteris IP has applied to list its common stock on the Nasdaq Global Market under the ticker symbol "AIP".

Topics: SoC interconnect IP NoC arteris ip K. Charles Janac IP market ip deployment Nick Hawkins Nasdaq S-1 SEC AIP intellectual property IP IPO