Arteris Press Releases

CAMPBELL, Calif. — March 8, 2017 — Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced its next generation automated interconnect timing solution – the PIANO 2.0 Timing Closure Package. PIANO 2.0 builds on customer silicon experience gathered with FlexNoC Physical^™ package to automate interconnect timing closure for both cache coherent and non-coherent subsystems.

By applying PIANO 2.0 together with generated placement guides, Renesas was able to close the complex SoC development sooner than we expected. Renesas has been an early user of Arteris’ closure technology, and we plan to continue to use Arteris’ enhanced closure capabilities for our future SoC developments.

Horst Rieger, Manager, Design Services, European Technology Center, Renesas Electronics Europe

Physically aware network-on-chip IP reduces timing closure effort and time-to-market

CAMPBELL, Calif. – Jan. 5, 2016 – Arteris Inc., the inventor and leading supplier of silicon-proven commercial Network-on-Chip (NoC) interconnect IP solutions, today announced that Renesas Electronics Europe has licensed Arteris^® FlexNoC Physical™ IP for use in its High-End SoC business division.

New version improves SoC designer productivity, provides foundation for future technologies

CAMPBELL, California — April 22, 2015 — Arteris Inc., the inventor and only supplier of silicon-proven commercial network-on-chip (NoC) interconnect IP solutions,  today announced availability of Arteris FlexNoC Physical interconnect IP, a breakthrough that accelerates system-on-chip (SoC) physical design.

Arteris is solving an important set of back-end problems with technology that works earlier in the SoC design flow. FlexNoC Physical IP has the potential to significantly decrease timing issues experienced in the layout stage, reducing P&R iterations and engineering change orders (ECOs) and saving cost and schedule time.

Mike Demler, Senior Analyst, The Linley Group

Arteris FlexNoC Physical has the promise to improve layout productivity by providing Synopsys tools, such as Design Compiler Graphical and IC Compiler II, with improved timing closure information and more accurate RTL data. We look forward to working with mutual customers to validate these propositions.

Bijan Kiani, Vice President of Marketing, Design Group, Synopsys