Ncore Cache Coherent Interconnect IP
High-Bandwidth, Low-Latency Network-on-Chip Interconnect
Solving Multi-Core Design Challenges With Safety Support
The key challenges in developing multi-core ASICs include managing complexity, power optimization, inter-core communication, synchronization, verification, testing, and performance optimization while ensuring scalability, reliability, and integration ease.
Ncore™ solves these challenges with a production-proven, highly configurable, and efficient coherent NoC interconnect IP solution that works with multiple protocols and any processors including Arm and RISC-V. Ncore offers unique value by being engineered to support ISO 26262 designs that, once certified, will ensure reliable operation in safety-critical applications with functional safety compliance.
The combined use of Ncore IP and FlexNoC IP in an ASIC design delivers unparalleled performance optimization, scalability, and system integration, enabling robust cache coherence, efficient communication, and flexibility, leading to market differentiation and accelerated time-to-market.
The Only Multi-Protocol AMBA CHI-B, CHI-E and ACE Cache Coherent NoC
Empowers SoC developers to create high-performance coherent SoC
Scalable
Ncore provides a high-bandwidth, low-latency interconnect fabric for efficient communication between different components of an SoC, offering scalable performance and power efficiency from small embedded systems to large multi-billion transistor designs.
Configurable
Multi-protocol coherency gives choice and reuse for legacy and future IP support. CHI-E, CHI-B, and ACE coherent as well as ACE-Lite IO coherent agent interfaces allow multiple initiator IPs to be connected to the same Ncore. Ncore also enables AXI non-coherent agents to act as IO coherent agents.
Safe
ISO -certified by an external assessor to ensure Ncore readiness for use in ISO 26262 -compliant chips from ASIL B to ASIL D, enabled by the Ncore Safety and Reliability product option. Automated generation of Fault Modes Effects and Diagnostic Analysis (FMEDA) data for your Ncore configuration.
Ncore Key Features
- Highly scalable system
- True heterogeneous coherency with mixed AMBA CHI and AMBA ACE support
- Full coherency for cached processors and I/O coherency for accelerators
- Configurable network and topologies
- Mesh topology with physical tiling of repetitive blocks
- Functional safety with FMEDA generation and ASIL D certification
- Configurable snoop filters
- I/O cache and system memory cache
- Lower power consumption
- Quality of Service (QoS)
- Debug & trace/monitoring
Feature Spotlight
NoC tiling - new feature with Ncore
NoC tiling with mesh topology for cache coherent CPUs. Up to 256 CPUs with 32-core cluster size.
- Scale performance
- Condense design time
- Speed testing
- Reduce design risk
- Supports Arm and RISC-V architectures
Create modular, scalable designs, enabling faster integration, verification and optimization.
Ncore Product Benefits
Higher Frequencies, Lower Latencies
Use of multiple configurable snoop filters to accommodate different cache organization
Lower Power Consumption
Fewer off-chip main memory accesses resulting in lower power consumption
Smaller Die Area
Fewer wires using optimal NoC transport layer
Easy Configuration
Ncore adapts to each coherent agent’s behavior and characteristics
Faster Time to Market
Tiling accelerates physical design, implementation and timing closure
Flexible Topologies
Choose from crossbar, mesh and ad-hoc topologies
Safety
Automate FMEDA safety documentation, ISO26262 ASIL B to D certified
Automated Verification
Saving hundreds of hours of work over manual verification generation
Shorter Schedules
Fewer iteration loops
Read more about why we are unique on our NoC Technology page.
Ncore Product Option
We are happy to share that we are partnering with Arteris to use Ncore and FlexNoC IP in our next-generation product. The combination of performance and features made it a great choice for both our AI chips and our high-performance RISC-V CPUs. The Arteris team and IP solved our on-chip network problems so we can focus on building our next-generation AI and RISC-V CPU products.
Tenstorrent – Ncore
Jim Keller, CEO, Tenstorrent
We chose the Arteris Ncore cache coherent interconnect because of its unique proxy caches and their ability to underpin high-performance, low power, cache coherent clusters of our unique AI accelerators. And with our prior experience using FlexNoC and the FlexNoC FuSa Option for functional safety, we trust Arteris to be the highest performing and safest choice for ISO 26262-compliant NoC IP.
Mobileye
Elchanan Rushinek, Vice President of Engineering, Mobileye
We are excited to partner with Arteris to accelerate the creation and delivery of an advanced communication SoC. Now, we can focus our resources where we bring the most value. Our company will leverage Arteris’ proven Ncore and FlexNoC technology and interconnect expertise for a combination that allows us to provide our customers with the best products in the shortest amount of time.
SCALINX – Ncore
Hussein Fakhoury, CEO of SCALINX
Arteris NoC technology enables wide on-chip bandwidth with fewer wires and lower latency than traditional bus and crossbar fabrics. This multiuse deal is expected to help us deliver these benefits more quickly to engineering teams throughout Freescale.
Freescale
Fares Bagh, Vice President of R&D, Freescale
We have worked with Arteris NoC technology since 2010, and are excited that Arteris has brought its significant engineering prowess to help solve the problems of fault tolerant and reliable SoC design.
Mobileye
Elchanan Rushinek, Vice President of Engineering, Mobileye
- Articles
- Reducing SoC Power With NoCs And Caches | Semiconductor Engineering
- All About NoCs | Electronic Design
- Accelerating SoC Evolution With NoC Innovations Using NoC Tiling for AI and Machine Learning | Design & Reuse
- Why NoC tiling matters in AI-centric SoC designs | EDN
- Cache Coherency In Heterogeneous Systems | Semiconductor Engineering
- SoC design: When a network-on-chip meets cache coherency | EDN
- Optimizing Communication and Data Sharing in Multi-Core SoC Designs | Design & Reuse
- Press Releases
- Arteris and MIPS Partner on High-Performance RISC-V SoCs for Automotive, Datacenter and Edge AI | Nov 12, 2024
- Arteris Network-on-Chip Tiling Innovation Accelerates Semiconductor Designs for AI Applications | Oct 15, 2024
- Arteris Expands Ncore Cache Coherent Interconnect IP To Accelerate Leading-Edge Electronics Designs | Mar 13, 2024
- Arteris Ncore Cache Coherent Interconnect IP Certified for ISO 26262 Automotive Functional Safety Standard | Nov 14, 2023
- Arteris Wins Autonomous Vehicle Technology of the Year Award | Oct 05, 2023
- Technical Papers
- Customers
- SCALINX and Arteris Partner on Advanced Communications Innovation | Dec 12, 2023
- Tenstorrent Selects Arteris IP for AI High-Performance Computing and Datacenter RISC-V Chiplets | May 02, 2023
- Ncore Licensed by Bitmain for Sophon TPU Artificial Intelligence (AI) Chips | July 09, 2019
- Ncore Implemented in Toshiba ISO 26262-Compliant ADAS Chip | June 11, 2019
- Ncore is Implemented by NXP | May 24, 2016
- Ecosystem
- Arteris Expands Automotive Solutions for Armv9 Architecture CPUs | Mar 13, 2024
- Semidynamics and Arteris Partner To Accelerate AI RISC-V System-on-Chip Development | Nov 02, 2023
- Fraunhofer IESE Partners With Arteris To Accelerate Advanced Network-on-chip Architecture Development for AI/ML Applications | Oct 17, 2023
- Arteris and SiFive Partner to Accelerate RISC-V SoC Design of Edge AI Applications | Feb 27, 2023
- Expanded Partnership Between Arteris and Arm to Accelerate Automotive Electronics | Sep 12, 2022
- Synopsys Delivers Industry’s First Cache Coherent Subsystem Verification Solution for Arteris Ncore Interconnect | May 24, 2016
- Industry Support for the Synopsys ARC-V Processor IP Portfolio
- Webinars
- Revolutionizing SoC Performance with Network-on-Chip Technology Bitcast
- Scaling Performance In AI Systems | Semiconductor Engineering
- How to Achieve Efficient Communication and Data Sharing in Multi-Core SoC Designs
- Arteris IP: A Flexible Multiprotocol Cache Coherent Network-on-Chip (NoC) for Heterogeneous SoCs | The Linley Group