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Ncore Cache Coherent Interconnect IP

High-bandwidth, low-latency network-on-chip (NoC) interconnect for rapid modular innovation.

Ncore Cache Coherent Interconnect IP

Overview

Solve multi-core design challenges with safety support

Built on more than a decade of volume silicon, Ncore™ is silicon-proven coherent NoC IP that is highly configurable, power-efficient, and works with any processor, including Arm® and RISC-V.

Extends full cache-coherency across chiplets for rapid, modular innovation.
ISO 26262 ASIL D ready.
Pairs with Magillem® automation for IP integration software, so teams can scale modular architectures, simplify multi-die design and compress development schedules.

Combining Ncore and FlexNoC gives designers foundational technology for unparalleled performance optimization, scalability, and system integration in an expanded multi-die solution. This enables robust cache-coherence, efficient communication, and flexibility, which can result in market differentiation and accelerated time-to-market.

Advantages

Create high-performance coherent SoCs

Scalable

Ncore provides a high-bandwidth, low-latency interconnect fabric for efficient communication between different components of an SoC and between multiple dies. This provides scalable performance and power efficiency from small embedded systems to large multi-billion transistor and multi-die designs.

Configurable

Multi-protocol coherency gives choice and reuse for legacy and future IP support. CHI-E, CHI-B, and ACE coherent, as well as ACE-Lite I/O coherent agent interfaces, allow multiple initiator IP to be connected to the same Ncore. Ncore also enables AXI non-coherent agents to act as I/O coherent agents.

Safe

ISO-certified by an external assessor to ensure Ncore readiness for use in ISO 26262 -compliant chips from ASIL B to ASIL D, enabled by the Ncore Safety and Reliability product option. Fault Modes Effects and Diagnostic Analysis (FMEDA) data is generated automatically for the Ncore configuration.

Ncore key features

Highly scalable system
True heterogeneous coherency with mixed AMBA CHI and AMBA ACE support
Full coherency for cached processors and I/O coherency for accelerators
Multi-die cache coherency over UCIe™ 1.1 via an AMBA CXS.B interface — up to four chiplets, and up to 4 × 128 GB/s links per die*
Configurable network and topologies
Mesh topology with physical tiling of repetitive blocks*
Functional safety with FMEDA generation and ASIL D certification*
Configurable snoop filters
I/O proxy cache and system memory cache
Low power consumption
Quality of service (QoS)
Debug and trace/monitoring

Show More Features

Explore additional Ncore features, download the datasheet.

* Denotes product option

Feature Spotlight

NoC tiling with Ncore

NoC tiling with mesh topology for cache coherent CPUs. Up to 256 CPUs with 8-core cluster size.

Scale performance
Condense design time
Speed testing
Reduce design risk
Supports Arm and RISC-V architectures

Create modular, scalable designs, with faster integration, verification, and optimization.

Ncore product benefits

Higher frequencies, lower latencies

Use of multiple configurable snoop filters to accommodate different cache organization.

Lower power consumption

Fewer off-chip main memory accesses result in lower power consumption.

Smaller die area

Fewer wires use the optimal NoC transport layer.

Easy configuration

Ncore adapts to each coherent agent’s behavior and characteristics.

Faster time to market

Tiling accelerates physical design, implementation, and timing closure.

Flexible topologies

Choose from crossbar, mesh, and ad-hoc topologies.

Safety

Automated FMEDA safety documentation and ISO26262 ASIL B to D certified.

Automated verification

Save hundreds of hours of work compared to manual verification generation.

Shorter schedules

Fewer iteration loops speed development time.

Ncore product options

Option

Resilience: Safety

ISO 26262 ASIL D Certified
Multi-ASIL support

Option

Multi-Die

Multi-die cache coherent option for Ncore up to four dies
Homogeneous and heterogeneous architectures
Fully-connected or mesh topologies
Pre-integrated with third-party UCIe 1.1 controller via AMBA CXS.B interface

Featured Solution

Multi-die solution accelerates AI-driven silicon innovation

Foundational technology for rapid chiplet-based design.

Flexible design scalability
Differentiated AI performance
Aligned with evolving industry standards

Built on silicon-proven NoC IP and Magillem® automation to scale modular architectures, the Arteris multi-die solution helps simplify multi-die projects, and compress development schedules.

Customer Testimonials

Trusted by innovative
 companies everywhere

We are happy to share that we are partnering with Arteris to use Ncore and FlexNoC IP in our next-generation product. The combination of performance and features made it a great choice for both our AI chips and our high-performance RISC-V CPUs. The Arteris team and IP solved our on-chip network problems so we can focus on building our next-generation AI and RISC-V CPU products.

We chose the Arteris Ncore cache coherent interconnect because of its unique proxy caches and their ability to underpin high-performance, low power, cache coherent clusters of our unique AI accelerators. And with our prior experience using FlexNoC and the FlexNoC FuSa Option for functional safety, we trust Arteris to be the highest performing and safest choice for ISO 26262-compliant NoC IP.

We are excited to partner with Arteris to accelerate the creation and delivery of an advanced communication SoC. Now, we can focus our resources where we bring the most value. Our company will leverage Arteris’ proven Ncore and FlexNoC technology and interconnect expertise for a combination that allows us to provide our customers with the best products in the shortest amount of time.

Arteris NoC technology enables wide on-chip bandwidth with fewer wires and lower latency than traditional bus and crossbar fabrics. This multiuse deal is expected to help us deliver these benefits more quickly to engineering teams throughout Freescale.

We have worked with Arteris NoC technology since 2010, and are excited that Arteris has brought its significant engineering prowess to help solve the problems of fault tolerant and reliable SoC design.

Resources

Datasheet

Ncore® Cache Coherent Interconnect Datasheet

Cache coherent network-on-chip (NoC) interconnect IP Arm® AMBA® CHI and ACE interoperability; CCIX protocol support for multi-chip systems
ISO 26262-compliant functional safety mechanisms

Case Studies