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Ncore Cache Coherent Interconnect IP

High-Bandwidth, Low-Latency Network-on-Chip Interconnect

Overview

Solving Multi-Core Design Challenges
With Safety Support

The key challenges in developing multi-core ASICs include managing complexity, power optimization, inter-core communication, synchronization, verification, testing, and performance optimization while ensuring scalability, reliability, and integration ease.

Ncore™ solves these challenges with a production-proven, highly configurable, and efficient coherent NoC interconnect IP solution that works with multiple protocols and any processors including Arm and RISC-V. Ncore offers unique value by being engineered to support ISO 26262 designs that, once certified, will ensure reliable operation in safety-critical applications with functional safety compliance.

The combined use of Ncore IP and FlexNoC IP in an ASIC design delivers unparalleled performance optimization, scalability, and system integration, enabling robust cache coherence, efficient communication, and flexibility, leading to market differentiation and accelerated time-to-market.

SoC Developers
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Advantages

The Only Multi-Protocol AMBA CHI-B, CHI-E and ACE Cache Coherent NoC

Empowers SoC developers to create high-performance coherent SoC

Scalable

Ncore provides a high-bandwidth, low-latency interconnect fabric for efficient communication between different components of an SoC, offering scalable performance and power efficiency from small embedded systems to large multi-billion transistor designs.

Configurable

Multi-protocol coherency gives choice and reuse for legacy and future IP support. CHI-E, CHI-B, and ACE coherent as well as ACE-Lite IO coherent agent interfaces allow multiple initiator IPs to be connected to the same Ncore. Ncore also enables AXI non-coherent agents to act as IO coherent agents.

Safe

ISO -certified by an external assessor to ensure Ncore readiness for use in ISO 26262 -compliant chips from ASIL B to ASIL D, enabled by the Ncore Safety and Reliability product option. Automated generation of Fault Modes Effects and Diagnostic Analysis (FMEDA) data for your Ncore configuration.

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Ncore Key Features

Ncore Key Features

Explore additional features of Ncore, download the datasheet.

Ncore Key Features
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Feature Spotlight

NoC tiling — new feature with Ncore

NoC tiling - new feature with Ncore

NoC tiling with mesh topology for cache coherent CPUs. Up to 256 CPUs with 32-core cluster size.

  • Scale performance
  • Condense design time
  • Speed testing
  • Reduce design risk
  • Supports Arm and RISC-V architectures

Create modular, scalable designs, enabling faster integration, verification and optimization.

Ncore Product Benefits

Higher Frequencies, Lower Latencies

Use of multiple configurable snoop filters to accommodate different cache organization

Lower Power Consumption

Fewer off-chip main memory accesses resulting in lower power consumption

Smaller Die Area

Fewer wires using optimal NoC transport layer

Easy Configuration

Ncore adapts to each coherent agent’s behavior and characteristics

Faster Time to Market

Tiling accelerates physical design, implementation and timing closure

Flexible Topologies

Choose from crossbar, mesh and ad-hoc topologies

Safety

Automate FMEDA safety documentation, ISO26262 ASIL B to D certified

Automated Verification

Saving hundreds of hours of work over manual verification generation

Shorter Schedules

Fewer iteration loops

Ncore Product Option

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Resilience: Safety Option
Option
Resilience: Safety
  • ISO 26262 ASIL D Certified
  • Multi-ASIL support
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Customer Testimonials

Trusted by innovative

companies everywhere

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Resources

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