Ncore Cache Coherent Interconnect IP
High-bandwidth, low-latency network-on-chip (NoC) interconnect IP for rapid modular innovation.
Overview
Solve multi-core and multi-die design challenges with safety support
Ncore is a configurable cache‑coherent interconnect with last‑level cache support that supports full CPU cache coherency and I/O coherency for high‑performance system designs.
Ncore Multi‑Die extends the Ncore coherent interconnect across multiple chiplets, enabling scalable, high‑performance architectures that overcome reticle limits and yield challenges, and addresses the growing requirement for modular compute and silicon process specialization in AI, automotive, HPC, and data‑centric SoCs.
Combining Ncore with FlexGen® or FlexNoC® provides designers with foundational technology for unparalleled performance optimization, scalability, and system integration in an expanded multi-die solution. This enables robust cache coherence, efficient communication, and flexibility, which can result in market differentiation and accelerated time to market.
Product Range
Ncore
Ncore
Multi-Die
Ncore
Efficient, low-power coherency up to 16 coherent initiators (with an available option for up to 32), as well as I/O coherency for high-performance I/O. Ncore offers true heterogeneous coherency, supporting both AMBA CHI and AMBA ACE processors, and can even coherently interwork between them utilizing the Arteris generic coherency protocol. It supports highly configurable last-level caches, helping to increase performance and reduce system power. The proxy cache eases integration of non-coherent accelerators into the coherent domain, simplifying software, increasing performance, and further reducing system power for AI/ML SoCs.
PCIe acceleration for high-performance PCIe devices, interfaced via a third-party PCIe controller, enables high-speed communications for AI, infrastructure, server, data center and HPC applications.
Automated generation of mesh topologies and physical tiling of logically equivalent NoC and processor element tiles eases physical design and reduces time-to-market
Ncore Multi-Die
Extends the coherent interconnect across two to four dies, enabling homogeneous performance scaling or coherent heterogeneous integration of differing chiplets for process optimization and specialization. Each Ncore Multi-Die chiplet contains an Ncore instance with up to 16 coherent initiators.
Ncore instances may have different configurations for each die. Ncore instances are linked together by Arteris multi-die technology to create a single, larger coherent interconnect spanning multiple chiplets, via pre-integrated and validated third-party UCIe controller and PHY interface IP.
ISO26262 ASIL B/D Certified Functional Safety
An available option across the entire Ncore product range, the Ncore Resilience and Safety package enables push-button ISO26262 ASIL functional safety (FuSa), which has been independently certified by Exida. Ncore automates the generation of FMEDA data, which is crucial for quantitatively predicting failure rates and demonstrating safety compliance of the entire system.
| Feature | Ncore MCU | Ncore Standard | Ncore Server | Ncore Multi-Die |
|---|---|---|---|---|
| Max fully-coherent ports | 2 | 8 | 16 | 16 (per die) |
| 32 coherent ports | ||||
| Max ACE-Lite and AXI Initiator ports | 2 | 2 | 2 | 2 |
| Last Level Cache | ||||
| Proxy Cache | ||||
| PCIe Acceleration | ||||
| Automated Mesh topology generation | ||||
| Tiling | ||||
| Coherent Multi-Die | ||||
| Resilience Package (FuSa) |
- Yes
- No
- Option
Advantages
Create high-performance coherent SoCs
Scale performance with multi-die coherency
By extending Ncore coherency across up to four dies, designers can scale performance linearly through homogeneous replication or mix heterogeneous compute resources using the best process technology for each domain. Coherency remains transparent to software, preserving standard programming models.
Configurable
Multi-protocol coherency gives choice and reuse for legacy and future IP support. CHI-E, CHI-B, ACE coherent, and ACE-Lite I/O coherent agent interfaces allow multiple initiator IP to be connected to the same Ncore. Ncore also enables AXI non-coherent agents to act as I/O coherent agents.
Increase bandwidth and reduce latency
With over 64 GB/s usable data bandwidth per link, and 256 GB/s per die, Ncore Multi‑Die provides the bandwidth needed for AI/ML and HPC workloads. Interleaving and link aggregation boost point‑to-point throughput, while message forwarding in the GIU minimizes latency.
Safe
ISO-certified by an external assessor to ensure Ncore readiness for use in ISO 26262 -compliant chips from ASIL B to ASIL D, enabled by the Ncore Resilience Option. Fault Modes Effects and Diagnostic Analysis (FMEDA) data is generated automatically for the specific Ncore configuration.
Tune systems for flexibility and design requirements
Support for mesh and fully connected homogeneous or heterogeneous chiplet interconnect topologies allows designers to tailor the system for performance, cost, or physical layout constraints. Logical‑to‑physical remapping enables die rotation or mirroring while maintaining correct routing, easing interposer design.
Ncore key features
- Highly scalable system
- True heterogeneous coherency with mixed AMBA CHI and AMBA ACE support
- Full coherency for cached processors and I/O coherency for accelerators
- Low power consumption
- Quality of service (QoS)
- Configurable snoop filters
- I/O proxy cache and last-level cache
- Configurable network and topologies
- Automated mesh topology generation with physical tiling of repetitive blocks
- Debug and trace/monitoring
- Optional Resilience package with FMEDA generation and ASIL D certification
Explore additional Ncore features, download the datasheet.
* Denotes product option
Ncore Multi-Die key features
- Cache coherency extended across 2 to 4 chiplets
- Link Ncore Multi-Die instances together into a single coherency domain
- Fully coherent die-to-die bridging via the gateway interface unit (GIU)
- Homogeneous and heterogeneous chiplet support
- AMBA CXS.B interface to UCIe controllers and PHYs
- Up to 4 UCIe 1.1 Advanced (4x 64 lanes@ 16 GT/s) die‑to‑die links per chiplet
- Up to 128 GB/s peak bandwidth per link (usable data bandwidth >64 GB/s / link)
- Mesh or fully connected (point-to-point) chiplet topologies
- Link remapping for die rotation and reflection, easing interposer routing
- Global NUMA address map with local‑optimized memory access
- Cross‑die DVM messaging for Arm System MMU control
- Pre‑integrated and verified with select UCIe controllers for faster time‑ to‑silicon
- Configuration of each unique chiplet and top-level chiplet connectivity within an intuitive graphical tooling environment
- Optional Resilience package with FMEDA generation
Explore additional Ncore Multi-Die features, download the datasheet.
Feature Spotlight
NoC tiling with Ncore
- Scale performance
- Condense design time
- Speed testing
- Reduce design risk
- Supports Arm and RISC-V architectures
Ncore product benefits
Higher frequencies, lower latencies
Use of multiple configurable snoop filters to accommodate different cache organization.
Reduced power consumption
Fewer off-chip main memory accesses result in reduced power consumption.
Small die area
Fewer wires using the optimal NoC transport layer.
Easy configuration
Every Ncore instance is unique, custom-crafted in configuration tooling for each SoC.
Accelerated time to market
Tiling accelerates physical design, implementation, and timing closure.
Flexible topologies
Choose from crossbar, mesh, or create a custom ad-hoc topology.
Safety
Automated FMEDA safety documentation and ISO26262 ASIL B to D certified.
Ncore Multi-Die product benefits
Easily access local and remote memory regions
The system-wide address map spans all chiplets, enabling seamless access to local and remote memory regions. NUMA semantics reduce latency for local accesses, improving performance per watt, and enabling highly efficient software scheduling.
Achieve robust and deadlock-free coherency across chiplets
Distributed DVM propagation ensures page‑table consistency across Arm SMMUs on different dies. A deadlock‑free routing scheme preserves system reliability even under high-coherency traffic.
Accelerate design integration and validation
Pre‑integration with select UCIe controllers accelerates bring‑up. The Arteris tool flow automatically partitions dies, configures each local Ncore instance, generates the global address map, and validates that the design is consistent and deadlock‑free, helping to reduce time to silicon.
Enable broad ecosystem compatibility
The GIU employs AMBA CXS.B, enabling interoperability with leading UCIe IP vendors and paving the way for support of future third‑party solutions. Ncore is CPU‑agnostic and supports Arm, RISC‑V, and other architectures.
Ncore product options
Multi-die solutions for the chiplet era
As AI systems move beyond a single die, Arteris keeps the architecture unified while silicon scales.
- Extend intelligent NoC data movement across die boundaries
- Preserve QoS, virtual channels and design intent
- Simplify chiplet integration with automation and security assurance
The Arteris multi-die solution helps engineering teams partition
systems across multiple dies while preserving architecture,
accelerating development and reducing integration risk.
Case Studies
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Quick Reference Guides
Frequently Asked Questions
What is cache-coherent NoC IP?
Cache-coherent NoC IP is a network-on-chip interconnect that maintains data consistency across multiple processors, accelerators, and memory subsystems in a SoC. It enables scalable, high-performance communication while ensuring all processing elements see the most up-to-date data.Lorem Ipsum is simply dummy text of the printing and typesetting industry. Lorem Ipsum has been the industry’s standard dummy text ever since the 1500s, when an unknown printer took a galley of type and scrambled it to make a type specimen book. It has survived not only five centuries, but also the leap into electronic typesetting, remaining essentially unchanged.
What types of SoC designs is Ncore best suited for?
Ncore is designed for complex SoC and multi-die systems that require high bandwidth, low latency, and scalable cache coherence. Typical use cases include AI and ML accelerators, automotive ADAS and autonomous driving platforms, data center SoCs, and high-performance embedded systems.
Does Ncore support Arm and RISC-V processors?
Yes. Ncore supports industry-standard processor architectures, including Arm® and RISC-V®, making it suitable for heterogeneous SoC designs that combine CPUs, GPUs, NPUs, and custom accelerators.
How does Ncore support multi-die and chiplet-based designs?
Ncore enables scalable cache coherence across multiple dies by supporting advanced interconnect topologies and industry-standard interfaces. This allows SoC architects to design chiplet-based systems while maintaining performance and data consistency across dies.
How does Ncore differ from traditional bus or crossbar interconnects?
Unlike traditional bus or crossbar architectures, Ncore provides scalable bandwidth and concurrency through a packet-based NoC architecture. This enables higher performance, better power efficiency, and greater scalability for large, complex SoCs.
What performance and scalability advantages does Ncore provide?
Ncore supports high core counts, multiple clock and power domains, and flexible topologies, allowing designers to scale performance without redesigning the interconnect. This helps future-proof SoC architectures as complexity increases.
Can Ncore be customized for specific SoC requirements?
Yes. Ncore is highly configurable, allowing designers to tailor topology, coherence domains, bandwidth, and power features to meet specific performance, power, and area (PPA) targets.
What tools and support are available with Ncore?
Ncore is supported by Arteris’ SoC integration and NoC design tools, which help architects model, configure, and validate interconnect designs. Arteris also provides technical support and services throughout the design cycle.
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