CodaCache Last-Level Cache IP
Overview
Ensure smooth data movement in modern SoC designs
CodaCache® addresses modern design challenges through performance-optimized caching, efficient data access, and power optimization techniques. It also effectively handles system scalability, SoC integration, timing closure, layout congestion, and real-time processing by providing scalable cache solutions, seamless integration capabilities, and support for real-time processing.
Using Arteris FlexGen, FlexNoC, FlexWay, and CodaCache IPs in the same SoC provides a unique high-performance, power-efficient, and scalable solution that meets the demanding requirements of modern SoC designs, while reducing development time, risk, and cost.
Advantages
Unlock the full potential of cache
Configurable systems
CodaCache configurability can fine-tune settings for optimal performance, unlocking the full potential of the cache in specific scenarios.
Increased performance
Facilitates fast and convenient access to frequently accessed data, eliminating the need to access the main memory and improving performance.
Seamless integration
AXI support results in efficient communication between components, easy integration into existing SoC designs, and accelerated development processes.
Features
CodaCache key features
- Flexible physical organization
- Associativity
- Per way configurable scratchpad memory
- Way partitioning
- Performance monitors
- Performance models
- Functional safety
- Graphical user interface (GUI)
- Assisted coherency management via hardware cache flush
Explore additional CodaCache features, download the datasheet.
Efficient data movement through the SoC
Combine with Arteris FlexGen®, FlexNoC® and FlexWay® for optimal agility:
- Ideal for NoC applications with data re-use.
- Improves overall SoC latency and power
Efficient data movement through the SoC
Benefits
CodaCache product benefits
Higher frequencies, lower latencies
Enhances system and IP performance through optimized caching and efficient data access.
Lower power consumption
Fewer off-chip main memory accesses, which results in reduced power consumption.
Smaller die area
This is achieved through a highly distributed architecture and configurable cache partitions.
Easy configuration
An intuitive and user-friendly interface helps accelerate setup.
Automated verification
Save hundreds of hours of work compared to manual verification generation.
Shorter schedules
Get to market faster than ever with streamlined processes.
Options
CodaCache product options
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- Up to 128 bytes
- Up to 256 bytes
- Up to 512 bytes
- ISO 26262 functional safety (FuSa)
- Multi-ASIL support
Resources
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- Arm & Arteris AI and ISO 26262 Presentation
- Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip (SoCs)
- FMEDA Automation for Scalability and Reuse in Complex Systems on Chips (SoCs)
- Is the Missing Safety Ingredient in Automotive AI Traceability?
- Safety Considerations for Network-on-Chip (NoC) Development
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