Non-Coherent Network-on-Chip IP Product Family
Build scalable SoCs faster with comprehensive non-coherent interconnect IP
Overview
Proven NoC IP for every SoC design point
The non-coherent network-on-chip IP product family brings together FlexGen®, FlexNoC®, and FlexWay® for modern SoC and chiplet development. From high-performance data center, AI, automotive, communications, consumer, enterprise, and industrial designs to cost-efficient MCUs and IoT edge devices, these solutions help teams select the right interconnect architecture for all performance, power, area, and schedule requirements.
- FlexGen smart NoC IP
AI-driven design automation for advanced SoCs and chiplets. FlexGen generates and refines optimized NoC topologies to minimize wirelength, latency, and design effort. - FlexNoC physically aware NoC IP
Comprehensive interconnect IP for complex SoCs. FlexNoC helps teams optimize interconnect performance, power, and area, while accelerating timing closure. - FlexWay low-power entry NoC IP
Entry-level NoC IP for cost-sensitive, low-power embedded SoCs, IoT edge devices, and MCUs.
Advantages
Flexible interconnect IP for modern SoC requirements
The non-coherent network-on-chip IP product family provides SoC teams with a scalable path from demanding, high-performance AI-driven designs to compact embedded devices. It combines automation, physical awareness, power management, and performance optimization in a single product family.
Match each design to the correct NoC
Select FlexWay for smaller low-power designs; FlexNoC for broad complex SoC development; or FlexGen when smart automation and faster design exploration are critical.
Improve performance and latency
Optimized data transport, quality-of-service (QoS) support, performance exploration tools, and smart topology generation help ensure efficient data movement across the SoC.
Reduce power, area, and wirelength
NoC architectures reduce long global wiring, support advanced power management, and help minimize routing congestion, die area, and latency.
Scale with product needs
Safety, reliability, reorder-buffer, XL, and 2XL options extend IP solutions for larger systems, functional safety, resilience, and memory performance.
Accelerate development cycles with FlexGen
FlexGen automated configuration, topology generation, and verification support help reduce repetitive work and shorten iteration loops.
Support physical convergence earlier with FlexGen and FlexNoC
Physical awareness, floorplan visualization, and auto-timing closure assistance help teams address implementation issues before late-stage place-and-route.
Features
Non-Coherent Network-on-Chip IP Product Family key features
Protocol, debug, verification, and integration
- Multi-protocol support, including AXI, AHB, APB, OCP, PIF, AMBA 5, and ACE-Lite, where product scope applies
- AMBA 5 support, including DVM 8.1, where applicable
- On-chip performance monitoring and debug
- Debug and trace with ATB 128b and timestamps
- Import and export with Magillem tools
- Integration with Magillem Connectivity, Magillem Registers, and CodaCache last-level cache
Scalability
- Support from small MCU-class designs to large SoCs and multi-die chiplet-based designs
- Multiple NoC instances where the product scope applies
- Optional mesh topology for NPUs, GPUs, and TPUs
- NIU tiling for modular, repeatable blocks
- Up to 1024 tiles in arrayed AI and accelerator designs
Intuitive configuration UI
Design automation and exploration with FlexGen
- Smart topology generation using AI-driven heuristics and machine-learning-assisted exploration
- Topology generation with minimum wirelength
- Scripting-driven regular topology creation
- Incremental design capability
Physical awareness and timing closure with FlexGen and FlexNoC
- Auto-timing closure assistance
- Topology visualization directly on the floorplan
- Support for faster convergence without late redesign loops
Performance, power, and area optimization
- Built-in NoC performance analysis and exploration tools
- Advanced QoS
- Power management through clock gating, DVFS, and GALS
- Unit-level clock gating
- Optimizations for performance, area, wire length, and latency
Feature Spotlight
NoC tiling for scalable AI and accelerator designs
FlexGen and FlexNoC support NoC tiling for highly scalable arrayed NPU, GPU, and TPU designs. Tiling helps teams create modular, repeatable architectures that can scale performance, speed testing, condense design time, and reduce design risk.
- Create modular, scalable designs.
- Use mesh topology for tiled accelerator architectures
- Support up to 1024 tiles
- Improve integration, verification, and optimization speed
Efficient data movement through the SoC
Integration with Arteris CodaCache® last-level cache raises the bar on innovation:
- Ideal for NoC applications with data re-use
- Improves overall SoC latency and power
Efficient data movement through the SoC
NoC integration automated flow
Automated flow to leverage SoC connectivity information using Arteris Magillem:
- Improved productivity with reduced process
- Better quality with early error detections thanks to checkers
NoC integration automated flow
Product comparison table
| Category | Features | FlexWay | FlexNoC | FlexGen |
|---|---|---|---|---|
| Target Audience and Scale | Smaller-scale MCU SoCs | |||
| Small-medium scale SoCs | ||||
| Large scale SoCs | ||||
| Instances Per Design | Single NoC instance | |||
| Multiple NoC instances | ||||
| Network Interface Units (NIUs) per die¹ | Up to 50 NIUs | |||
| Up to 200 NIUs | ||||
| Up to 1000 NIUs | with XL option | with XL option | ||
| Up to 2000 NIUs | with 2XL option | with 2XL option | ||
| Compatibility | AXI, AHB, APB, OCP, PIF, AMBA5 | |||
| ACE-Lite | ||||
| Smart NoC Automation | Topology generation with minimum wire length | |||
| Scripting-driven regular topology creation | ||||
| Incremental design capability | ||||
| Physical Awareness | Automatic timing closure assistance | |||
| Floorplan visualization | ||||
| Advanced Scalability |
Spine Tiling2,3 | with XL/2XL options | with XL/2XL options | |
| Mesh topology editor | with XL/2XL options | with XL/2XL options | ||
| Write broadcast stations | with XL/2XL options | with XL/2XL options | ||
| Virtual channel links | with XL/2XL options | with XL/2XL options | ||
| Source synchronous asynchronous bridges | with XL/2XL options | with XL/2XL options | ||
| Up to 1024 bits data bus | with XL option | with XL option | ||
| Up to 2048 bits data bus | with 2XL option | with 2XL option | ||
| 512 pending transaction support | with XL option | with XL option | ||
| 1024 pending transaction support | with 2XL option | with 2XL option | ||
| Optimizations | Optimization for performance, area and wire length | |||
| Advanced Quality of Service (QoS) | ||||
| Power management and security | ||||
| Address and data protection schemes | ||||
| Advanced in-circuit debug features | ||||
| Multi-cycle SRAM support | ||||
| Floorplan visualization | ||||
| Add-on Options | Memory Re-order Buffer option | |||
| Reliability option | ||||
| Safety (up to ISO 26262 ASIL D) option | ||||
| Advanced Scalability (XL/2XL) options | ||||
| Markets | Automotive, Aerospace & Defence, Communications, Consumer Electronics, Enterprise Computing and Industrial Markets |
¹ NIU limits apply per individual monolithic die or chiplet design.
² FlexGen is advised for customers seeking to create a mesh topology using tiling.
³ Customers seeking to license multiple optional features should disclose its requirements to Arteris support engineers. Given the increasing complexity of designs, customers are advised to communicate their specific design needs to Arteris support engineers.
Fully integrated product options
- NIU tiling
- Mesh topology editor
- Up to 2048 bits data bus
- Virtual channel links
- Write broadcast stations
- Up to 1024 pending transactions
- ISO 26262 Functional Safety (FuSa)
- Multi-ASIL support
- Interconnect-wide ECC support
Single and multichannel reorder buffers (ROB):
- Avoid ordering rule blocks
- Avoid response serialization bottlenecks
- Allow concurrent memory channel reads
Multi-die solution accelerates AI-driven silicon innovation
- Flexible design scalability
- Differentiated AI performance
- Aligned with evolving industry standards
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