FlexGen Smart Network-on-Chip (NoC) IP
Overview
Intelligent automation for next-gen SoC design
Arteris FlexGen® introduces cutting-edge AI heuristics and machine learning, automating NoC topology generation to achieve up to 10x faster design iterations than traditional methods.
- Optimize wire length.
- Reduce latency.
- Improve power efficiency.
- Minimize manual intervention.
Designed for automotive, data centers, and industrial electronics applications, FlexGen shortens design cycles, enabling faster time-to-market and/or multiple design explorations for the most complex systems.
Advantages
The smart and efficient way to build SoCs
10x productivity boost
Smart NoC generation is 10x faster than traditional NoC flows, shortening SoC or chiplet iterations from weeks to days for design efficiency.
Expert-level results
Minimal effort for top-quality results and three times improvement in engineering efficiency across all NoCs. Algorithms minimize routing congestion, improving silicon area during physical design, with proven links to physical synthesis, place, and route to support tape-out success.
Wire length reduction-driven performance
Smart AI heuristics using machine-learning technology deliver an optimized topology with an average wire length reduction of up to 30%, reducing overall latency by up to 10%, and delivering power improvements across the design.
Features
FlexGen key features
- Smart NoC automation
- Topology generation with minimum wire length
- Scripting-driven regular topology creation
- Incremental design capability
- Auto-timing closure assist
- … plus all the key features of FlexNoC 5
Explore additional FlexGen features, download the datasheet.
Feature Spotlight
NoC tiling with FlexGen
NoC tiling with mesh topology for NPUs, GPUs, TPUs with FlexGen. Up to 1024 tiles.
- Scale performance
- Condense design time
- Speed testing
- Reduce design risk
Create modular, scalable designs, with faster integration, verification and optimization.
Efficient data movement through the SoC
Integration with Arteris CodaCache® last-level cache raises the bar on innovation:
- Ideal for NoC applications with data re-use
- Improves overall SoC latency and power
Efficient data movement through the SoC
NoC integration automated flow
Automated flow to leverage SoC connectivity information using Arteris Magillem:
- Improved productivity with reduced process
- Better quality with early error detections thanks to checkers
NoC integration automated flow
Benefits
FlexGen product benefits
Expert-level output quality
Generated smart NoC architecture and physical constraints.
Significant reductions in wire length
Minimize die area, power consumption, and latency.
10x productivity improvement
Reduce setup and configuration time from days to hours or minutes by automating repetitive, time-intensive tasks.
Higher frequencies, lower latencies
Use built-in NoC performance analysis exploration tools.
Speedy timing closure
Early physical awareness results in faster convergence without re-designs.
Automated verification
Save hundreds of hours of work versus manual verification test benches.
Increased profit
Reduce time to market with FlexGen design efficiency savings.
Options
FlexGen fully integrated product options
- NIU tiling
- Mesh topology editor
- Up to 2048 bits data bus
- Virtual channel links
- Write broadcast stations
- ISO 26262 Functional Safety (FuSa)
- Multi-ASIL support
- Interconnect-wide ECC support
Single and multichannel reorder buffers (ROB):
- Avoid ordering rule blocks
- Avoid response serialization bottlenecks
- Allow concurrent memory channel reads
Multi-die solution accelerates AI-driven silicon innovation
- Flexible design scalability
- Differentiated AI performance
- Aligned with evolving industry standards
Resources
- FlexGen® Smart Interconnect IP Datasheet
- FlexGen, FlexNoC & FlexWay Functional Safety (FuSa) Option Datasheet
- FlexGen, FlexNoC & FlexWay Reliability Option for Enterprise Applications Datasheet
- FlexGen, FlexNoC & FlexWay Reliability Option for Industrial Applications Datasheet
- FlexGen, FlexNoC & FlexWay Re-Order Buffer (ROB) Option Datasheet
- FlexGen and FlexNoC XL and 2XL Option Datasheet
- SemiWiki: How NoC Tiling Capability is Changing the Game for AI Development with Andy Nightingale
- EE Times: Automating NoC Design Masters SoC Complexity
- EE Journal: Managing the Massive Data Throughput: AI-Based Designs and The Value of NoC Tiling
- EE Journal: The Network-on-Chip Pioneer: How Arteris Enabling SoC Developers to Create Physically Valid NoCs Faster
- Electronic Design: All About NoCs
- SemiWiki: The Impact of Arteris on Automotive and Beyond with Frank Schirrmeister
- SemiWiki: A Broad View of Design Architectures and the Role of the NoC with Arteris’ Michal Siwinski
- EE Journal: The Freedom to Innovate: Arteris and the Rise of RISC-V
- SemiWiki: The Impact of Using a Physically Aware NoC with Charlie Janac
- Arm & Arteris AI and ISO 26262 Presentation
- Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip (SoCs)
- Building Better IP with RTL Architect NoC IP Physical Exploration
- Efficient Scaling of AI Accelerators Using NoC Tiling
- FMEDA Automation for Scalability and Reuse in Complex Systems on Chips (SoCs)
- Is the Missing Safety Ingredient in Automotive AI Traceability?
- Lessons Learned Integrating AI/ML Accelerators into Complex ISO 26262 Compliant Systems-on-Chip
- Safety Considerations for Network-on-Chip (NoC) Development
- The Role of Networks-on-Chips Enabling AI/ML Silicon and Systems
- Tiled Approach to System Scaling
- Smart NoC Automation: Accelerating AI-Ready SoC Design in the Era of Chiplet
- FlexGen Smart NoC IP from Arteris Revolutionizes Complex SoC Designs
- Accelerating Timing Closure for Networks-on-Chip (NoCs) using Physical Awareness
- Chiplets: Opportunities and Challenges
- NoC-Centric System Performance for the Chiplet-Era with Platform Architect
- Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications
- Revolutionizing Semiconductor Design with Smart NoC IP
- FlexGen Product Tour
- Integration Challenges for RISC-V Designs
- Promises and Pitfalls of SoC Restructuring
- Scaling Performance in AI Systems
- Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product
- Power Dissipation of the Network-on-Chip in a System-on-Chip for MPEG-4 Video Encoding
- Re-Architecting SoCs for the AI Era
- Scalability – A Looming Problem in Safety Analysis
- Security in Artificial Intelligence
- Using Machine Learning for Characterizations of NoC Components
- Using Virtual Prototypes to Improve the Traceability of Critical Embedded Systems Flow
- Boost SoC Efficiency and Speed with FlexGen Smart NoC IP Automation White Paper
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