FlexGen Smart Network-on-Chip (NoC) IP
AI-enhanced automation for smarter multi-die SoC and chiplet designs.
Overview
Intelligent automation for next-gen SoC design
Arteris FlexGen® smart NoC IP automates NoC topology generation, while FlexGen Multi-Die extends these capabilities across die boundaries with die-to-die controller IP for chiplet-to-chiplet interconnect.
Using cutting-edge AI heuristics and machine learning, FlexGen accelerates design iterations by up to 10x compared with traditional manual NoC design methods across monolithic and multi-die designs.
- Optimize wire length.
- Reduce latency.
- Improve power efficiency.
- Efficiently connect FlexGen NoCs from chiplet to chiplet.
- Minimize manual intervention.
Designed for high performance compute (HPC) and AI accelerator applications for data centers, automotive, consumer, and industrial electronics applications, FlexGen shortens design cycles, enabling faster time-to-market and multiple design explorations for the most complex systems.
Advantages
The smart and efficient way to build SoCs
10x productivity boost
Smart NoC generation is 10x faster than traditional NoC flows, shortening SoC or chiplet iterations from weeks to days for design efficiency.
Expert-level results
Minimal effort for top-quality results and three times improvement in engineering efficiency across all NoCs. Algorithms minimize routing congestion, improving silicon area during physical design, with proven links to physical synthesis, place, and route to support tape-out success.
Wire length reduction-driven performance
Smart AI heuristics using machine-learning technology deliver an optimized topology with an average wire length reduction of up to 30%, reducing overall latency by up to 10%, and delivering power improvements across the design.
Chiplet ready, multi-die interconnect
The FlexGen die-to-die controller packages the NoC transport protocol using a highly configurable FLIT format to maximize PHY flexibility and minimize bandwidth overhead, latency, area, and power, and can be used with a wide variety of third party industry standard PHYs, including UCIe and BoW.
FlexGen key features
- Smart NoC automation
- Topology generation with minimum wire length
- Scripting-driven regular topology creation
- Incremental design capability
- Auto-timing closure assist
- Die-to-die controller with highly configurable FLIT format, supporting up to eight independent receive and transmit virtual channels with credited links.
- … plus all the key features of FlexNoC 5
Explore additional FlexGen features, download the datasheet.
Feature Spotlight
NoC tiling with FlexGen
NoC tiling with mesh topology for NPUs, GPUs, TPUs with FlexGen. Up to 1024 tiles.
- Scale performance
- Condense design time
- Speed testing
- Reduce design risk
Create modular, scalable designs, with faster integration, verification and optimization.
Efficient data movement through the SoC
Integration with Arteris CodaCache® last-level cache raises the bar on innovation:
- Ideal for NoC applications with data re-use
- Improves overall SoC latency and power
Efficient data movement through the SoC
NoC integration automated flow
Automated flow to leverage SoC connectivity information using Arteris Magillem:
- Improved productivity with reduced process
- Better quality with early error detections thanks to checkers
NoC integration automated flow
FlexGen product benefits
Expert-level output quality
Generated smart NoC architecture and physical constraints.
Significant reductions in wire length
Minimize die area, power consumption, and latency.
10x productivity improvement
Reduce setup and configuration time from days to hours or minutes by automating repetitive, time-intensive tasks.
Higher frequencies, lower latencies
Use built-in NoC performance analysis exploration tools.
Speedy timing closure
Early physical awareness results in faster convergence without re-designs.
Automated verification
Save hundreds of hours of work versus manual verification test benches.
Increased profit
Reduce time to market with FlexGen design efficiency savings.
PHY agnostic D2D controller
Highly configurable FLIT format supports a wide variety of third party industry standard PHY IP, e.g. UCI, BoW, etc.
Product comparison table
| Category | Features | FlexWay | FlexNoC | FlexGen | FlexGen Multi-Die |
|---|---|---|---|---|---|
| Target Audience and Scale | Smaller-scale MCU SoCs | ||||
| Small-medium scale SoCs | |||||
| Large scale SoCs | |||||
| Multi-Die SoCs | |||||
| Instances per Design | Single NoC instance | ||||
| Multiple NoC instances | |||||
| Network Interface Units (NIUs) | Up to 50 NIUs | ||||
| Up to 200 NIUs | |||||
| Up to 1000 NIUs | XL option | XL option | XL option | ||
| Up to 2000 NIUs | 2XL option | 2XL option | |||
| Compatibility | AXI, AHB, APB, OCP, PIF, AMBA 5 | ||||
| ACE-Lite | |||||
| Smart NoC Automation | Topology generation with minimum wire length | ||||
| Scripting driven regular topology creation | |||||
| Incremental design capability | |||||
| Wire congestion statistics reporting option | Included | ||||
| Physical Awareness | Automatic timing closure assistance | ||||
| Floorplan visualization | |||||
| Chiplet-to-Chiplet NoC connectivity | PHY agnostic FlexGen Die-to-Die IP | ||||
| Adapator layer for third-party PHY | Coming soon | ||||
| Advanced Scalability | Enhanced Tiling (partial network)1,2 | XL option | XL/2XL options | XL/2XL options | |
| Mesh topology editor | XL option | XL/2XL options | XL/2XL options | ||
| Write broadcast stations | XL option | XL/2XL options | XL/2XL options | ||
| Virtual channel links | XL option | XL/2XL options | XL/2XL options | ||
| Source synchronous asynchronous bridges | XL option | XL/2XL options | XL/2XL options | ||
| Up to 1024 bits data bus | XL option | XL option | XL option | ||
| Up to 2048 bits data bus | 2XL option | 2XL option | |||
| 512 pending transaction support | XL option | XL option | XL option | ||
| 1024 pending transaction support | 2XL option | 2XL option | |||
| Optimizations | Optimization for performance, area, and wire length | ||||
| Advanced quality of service (QoS) | |||||
| Power management and security | |||||
| Address and data protection schemes | |||||
| Advanced in-circuit debug features | |||||
| Multi-cycle SRAM support | |||||
| Add-On Options | Memory Reorder Buffer Option | ||||
| Reliability Option | |||||
| Safety (up to ISO 26262 ASIL-D) Option | |||||
| Advanced Scalability Options (XL and 2XL) |
¹ FlexGen is advised for customers seeking to create a mesh topology using tiling.
² Customers seeking to license multiple optional features should disclose its requirements to Arteris support engineers. Given the increasing complexity of designs, customers are advised to communicate their specific design needs to Arteris support engineers.
FlexGen fully integrated product options
- Enhanced tiling
- Mesh topology editor
- Up to 2048 bits data bus
- Virtual channel links
- Write broadcast stations
- ISO 26262 Functional Safety (FuSa)
- Multi-ASIL support
- Interconnect-wide ECC support
Single and multichannel reorder buffers (ROB):
- Avoid ordering rule blocks
- Avoid response serialization bottlenecks
- Allow concurrent memory channel reads
Multi-die solutions for the chiplet era
As AI systems move beyond a single die, Arteris keeps the architecture unified while silicon scales.
- Extend intelligent NoC data movement across die boundaries
- Preserve QoS, virtual channels and design intent
- Simplify chiplet integration with automation and security assurance
The Arteris multi-die solution helps engineering teams partition
systems across multiple dies while preserving architecture,
accelerating development and reducing integration risk.
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Quick Reference Guides
Frequently Asked Questions
What is FlexGen Smart NoC IP?
FlexGen is an AI-driven smart Network-on-Chip (NoC) interconnect IP that automates optimized interconnect topology generation for complex SoC and chiplet designs, improving productivity and performance.
How does FlexGen improve SoC design productivity?
FlexGen leverages AI and machine learning to generate interconnect topologies automatically, reducing repetitive manual design iterations and enabling up to a 10× faster workflow.
What performance improvements can FlexGen deliver?
FlexGen reduces wire length by up to 30%, lowers interconnect latency, and improves engineering throughput with expert-level results.
What industries benefit most from FlexGen?
FlexGen is suitable for automotive SoCs, AI and machine learning accelerators, data center silicon, industrial electronics, and other high-complexity semiconductor designs.
Does FlexGen support safety-critical applications?
FlexGen offers options that support ISO 26262 functional safety, making it suitable for safety-critical automotive and industrial applications.
What is the difference between FlexGen and FlexNoC?
FlexGen adds AI-based automation for smart NoC generation, while FlexNoC focuses on physically aware NoC interconnect with reduced turn-around time for manual design flow integration. This comparison helps guide keyword relevance and internal linking.
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