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FlexGen Smart Network-on-Chip (NoC) IP

AI-Enhanced Automation for Smarter SoC Design

FlexGen Smart NoC IP

Overview

Revolutionizing SoC Design with Intelligent
Automation

FlexGen^TM by Arteris redefines how SoC designers create Network-on-Chip IP by introducing cutting-edge AI heuristics and machine learning. This revolutionary IP automates NoC topology generation, achieving up to 10x faster design iterations than traditional methods.

With FlexGen, teams can optimize wire length, reduce latency, and improve power efficiency while minimizing manual intervention. Designed for automotive, data centers, and industrial electronics applications, FlexGen shortens design cycles, enabling faster time-to-market and/or multiple design explorations for the most complex systems.

Advantages

The Smarter Way to Build SoCs

Redefining productivity and efficiency in SoC design

10x Productivity Boost

Smart NoC generation is 10x faster than traditional NoC flows, shortening SoC or chiplet iterations from weeks to days for design efficiency.

Expert Level Results

3x improvement in engineering efficiency with expert quality of results with minimal effort across all NoCs. Algorithms minimize routing congestion, improving silicon area during physical design, with proven links to physical synthesis and place and route to support tapeout success.

Wire Length Reduction Driven Performance

Smart AI heuristics using machine-learning technology delivers an optimized topology with an average wire length reduction of up to 30%, reducing overall latency by up to 10%, plus power improvements across the design.

FlexGen Key Features

Smart NoC automation
Topology generation with minimum wire length
Scripting-driven regular topology creation
Incremental design capability
Auto-timing closure assist
… plus all the key features of FlexNoC 5

Explore additional features of FlexGen, download the datasheet.

Feature Spotlight

NoC tiling — new feature with FlexNoC

NoC tiling with mesh topology for NPUs, GPUs, TPUs with FlexNoC. Up to 1024 tiles.

Scale performance
Condense design time
Speed testing
Reduce design risk

Create modular, scalable designs, enabling faster integration, verification and optimization.

Efficient Transport of Data Through the SoC

Arteris CodaCache® last-level cache:

Ideal for NoC applications with data re-use
Improves overall SoC latency and power

Efficient Transport of Data Through the SoC

NoC Integration Automated Flow

Automated flow to leverage SoC connectivity information:

Improved productivity with reduced process
Better quality with early errors detections thanks to the checkers

NoC Integration Automated Flow

FlexGen Product Benefits

Expert Level Output Quality

Generated smart NoC architecture and physical constraints

Significant Reductions in Wire Length

Minimizes die area, power consumption, and latency

10x Productivity Improvement

Reducing setup and configuration time from days to hours or minutes by automating repetitive, time-intensive tasks

Higher Frequencies, Lower Latencies

Using built-in NoC performance analysis exploration tools

Speedy Timing Closure

Early physical awareness for faster convergence without re-designs

Automated Verification

Saving hundreds of hours of work versus manual verification test benches

Higher Profit

Reduced TTM from FlexGen design efficiency savings

FlexGen Product Options

Seamlessly integrated extensions to the base FlexGen feature set

Option

Large Systems: XL

NIU tiling
Mesh topology editor
Up to 1024 bits data bus
Virtual channel links
Write broadcast stations

Option

Resilience: Safety

ISO 26262 Functional Safety (FuSa)
Multi-ASIL support
Interconnect-wide ECC support

Option

Performance: Reorder Buffer

Single and Multi-channel reorder buffers (ROB):

Avoid ordering rule blocks
Avoid response serialization bottlenecks
Allow concurrent memory channel reads

Customer Testimonials

Trusted by innovative
companies everywhere

FlexGen’s AI-based automation has streamlined our design processes, delivering shorter wire lengths and lower latencies.

Using Arteris FlexNoC allows us to reduce development time and manage project risk. FlexNoC’s advanced quality-of-service and debugging features, combined with its multi-protocol support, allow Samsung SUHD TVs to reduce power consumption and die area for complex chips with more than 100 IP interfaces.

Reliable and fast design capture: tedious tasks are hidden for the SoC integrator.

Our successful adoption of Arteris FlexNoC fabric IP has been straightforward, allowing us to more quickly architect and implement sophisticated systems-on-chip in less time and with better power consumption and performance.

We automatically generated 2 Million lines of register header files for just one chip! And we automated much of our Linux device tree and low-level firmware development.

We selected Arteris interconnect IP technology and SoC integration software to optimize product performance, minimize latency and accelerate the creation and delivery of our AI accelerator. Arteris is a leader in system IP and their FlexNoC interconnect IP and Magillem software are synergistic with our vision for the future of AI computing.

…we are finding that hardware data protection within the interconnect is increasingly required to meet our desired ISO 26262 ASIL levels. In our never-ending efforts to improve efficiency, we’ve found Arteris technology is helping us meet our safety and time-to-market goals.

With Arteris, our customers can be assured of responsiveness and reliability to help reduce collisions and make roads safer.

The Arteris FlexNoC interconnect IP helps us greatly by enabling not only high bandwidth on-chip communications but also load-balanced data traffic to off-chip memory, all while simplifying our backend timing closure. In addition, Arteris IP’s strong local support team has been a trusted partner in our AI chip development projects.”

Resources

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Infographic

Accelerating Timing Closure for Networks-on-Chip (NoCs) With Physical Awareness

Webinar

Video

Case Study

Dream Chip Case Study

Presentation

Podcast

White Paper

Datasheet

FlexGen™ Smart Interconnect IP Datasheet

What's New

Latest News

Press Releases

Arteris Revolutionizes Semiconductor Design with FlexGen – Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results

Arteris revolutionizes semiconductor design with smart network-on-chip (NoC) interconnect IP. FlexGen from Arteris dramatically accelerates chip development while optimizing performance efficiency, addressing the rising demand for faster, more sustainable innovation in automotive, datacenter, consumer electronics, communications and industrial applications.

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FlexGen Smart Network-on-Chip (NoC) IP