The world's #1 on-chip fabric is used by the world's top semiconductor design teams as the backbone on-chip communications for chips targeting the fastest growing markets.
The latest generation FlexNoC 5 Interconnect with its integrated physical awareness technology, gives place and route teams a much better starting point while simultaneously reducing interconnect area and power consumption. FlexNoC 5 delivers up to 5X shorter turn-around-time versus manual physical iterations.
Everything design teams need to create the world's best SoCs, faster
FlexNoC is generated from simple elementary components which are combined by a powerful set of underlying algorithms and an intuitive GUI, making it possible to build any topology.
FlexNoC easily supports long cross-chip paths by leveraging source-synchronous communications and virtual channels.
FlexNoC drives performant on-chip data flow and access to off-chip memory by enabling multi-channel HBM2 memory and high bandwidth data paths.
Automated flow to leverage SoC connectivity information:
Learn about Magillem Connectivity and Magillem Registers
Using built-in NoC performance analysis exploration tools
Advanced power management through clock gating, DVFS
Fewer wires using optimal NoC transport layer
Early physical awareness for faster convergence without
Through the intuitive
FlexNoC 5 UI
Saving hundreds of hours of work versus manual verification test benches
Fewer iteration loops
Reduced TTM from FlexNoC design efficiency savings
Read more about why we are unique on our NoC Technology page.
Sondrel has deployed Arteris FlexNoC interconnect IP across several customer SoC projects to great effect. Physical constraints have always been an important issue and are even more important below 16nm geometries. The latest FlexNoC 5 with its physical awareness technology, enables our RTL teams to verify that architectures meet physical constraints and provide a better starting point for our place and route team. We look forward to our continued cooperation with Arteris.