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Magillem Platform

Build complex SoCs faster with a unified design environment

Magillem Platform

Overview

Unified design flow accelerates time to revenue

The Arteris Magillem Platform provides a unified, end-to-end design flow for a radically improved development process that is seamless, fast, and helps reduce risk. Each step in the design flow is simplified:

Magillem Packaging: Eases content reuse and integration from different sources, thanks to standards-based IP description automation with the built-in ability to validate incoming data, helping to ensure IP Integrity.
Magillem Connectivity: Streamlines and accelerates SoC assembly with a robust and portable design process that can be used by all teams, maximizing collaborative work and data accuracy.
Magillem Registers: Completing the integration flow, it addresses hardware and software interface automation to help ensure the address map is self-consistent and the auto-generated collaterals are of the highest quality, minimizing risks downstream.

Aligned through a unified integration environment, this fully automated design flow helps increase productivity and quality.

Advantages

Effective design collaboration for modern SoCs

The Magillem platform provides an automated design flow and allows all relevant teams to collaborate effectively. This helps accelerate SoC development, while mitigating design risks.

Smooth and efficient process

Powerful automation helps reduce effort, rework, and errors

Promote design reuse

A true IP re-use methodology helps improve efficiency and quality.

Shorten time to market

Accelerating SoC connectivity and HSI development helps bring projects to market faster than ever.

Derisk SoC design

The unified environment helps ensure accuracy and cross-team consistency.

Improved quality

Robust error checking helps developers fix bugs early in the design process.

Productivity gains

Efficient automated processes help free engineers from repetitive tasks to focus on true innovation.

Features

Magillem Platform key features

SoC integration and platform assembly

IP and design reuse

Hardware/software interface – register management

Design flow automation – CAD flow

Products for the Magillem Platform

SoC Connectivity

Magillem Packaging

A fully automated solution to import legacy RTL and create a correct by-construction IP-XACT description, map the physical ports into the bus interface, and capture the memory map.

Hardware / Software Interface

Magillem Registers

Importing the memory map description in Magillem Registers helps ensure synchronization between hardware, software, and documentation for automatic, consistent data generation.

SoC Connectivity

Magillem Connectivity

Automation tools and built-in checkers to boost productivity, accelerate TTM and improve design quality, while shortening, streamlining, and de-risking the integration process.

Magillem Platform

Powerful comprehensive SoC integration automation

Category	Features	Magillem Packaging	Magillem Connectivity	Magillem Registers
IP-XACT Conversion	2009 to 2022
IP-XACT Conversion	2014 to 2022
Resource Management	Projects
	Catalogs
	Components
TGI	TGI API
HDL Import	Verilog/SystemVerilog support
HDL Import	View & FileSet elaboration
Bus Interface	Auto mapping
Rules Checkers	Design and component
	Memory and system map
	Configurable checker severity
Assembly	Rule-based connectivity
	Bus/signal split/tie/open/feedthrough
	Glue logic insertion
RTL Netlist Generation	Configurable header
	Keep parameter expressions
	Signals/netname/tie management
Hierarchical Manipulations	Merge, Flatten, Move operations
Hierarchical Manipulations	Parameter propagation
IP Update	Rename/resize/delete/merge
IP Update	User mapping rules definition
Diff and Merge	Accept/Reject any change
Diff and Merge	Conflict resolution wizard
Import Memory Map Description	SystemRDL support
	IP-XACT support
	Excel spreadsheets support
Generate HSI Outputs	RTL register bank (VHDL, Verilog, SystemVerilog)
	Customized C Header files
	UVM RAL files
	Documentation (Word, FrameMaker, HTML)
	SystemRDL description
	IP-XACT description

Full NoC integration for automated flow

Leverage SoC connectivity information:

Increase productivity with reduced process.
Improve quality with early error detection by checkers.

NoC Integration Automated Flow

Customer Testimonials

Trusted by innovative
 companies everywhere

Reliable and fast design capture: tedious tasks are hidden for the SoC integrator.

Using Arteris FlexNoC allows us to reduce development time and manage project risk. FlexNoC’s advanced quality-of-service and debugging features, combined with its multi-protocol support, allow Samsung SUHD TVs to reduce power consumption and die area for complex chips with more than 100 IP interfaces.

Reliable and fast design capture: tedious tasks are hidden for the SoC integrator.

Our successful adoption of Arteris FlexNoC fabric IP has been straightforward, allowing us to more quickly architect and implement sophisticated systems-on-chip in less time and with better power consumption and performance.

Resources

White Paper

Making SoC Integration Simple – Achieve Higher Productivity and Quality

This paper explores engineers’ challenges, how Arteris can help, and why such solutions will not only benefit design teams in the short run by boosting their productivity and achieving successful tape-outs but will also result in long-term savings as the teams are free to focus on the core business and leverage their technical expertise where it matters most.

Datasheets

Infographics

Simplifying SoC Integration with Arteris

Podcasts

Presentations

Solution Briefs

Accelerate and Optimize AI-Based SoC Designs with Arteris

Videos

Webinars

White Papers

Featured Solution

Arteris accelerates AI-driven silicon innovation with its expanded multi-die solution

Foundational technology for rapid chiplet-based design.

Flexible design scalability
Differentiated AI performance
Aligned with evolving industry standards

Built on silicon-proven NoC IP and Magillem™ automation to scale modular architectures, simplify multi-die projects, and compress development schedules.