Automate SoC Assembly to
Eliminate Tedious Tasks and
Focus on What Matters Most

For design teams coping with exploding complexity, the Magillem® Connectivity product streamlines and shortens by 30% the integration process to create correct by construction platforms.

It accelerates IPs deployment with continuous integration for an automated hardware development flow adapting to changes.

automate SoC assembly

Reduce the Integration Process
From Months to Weeks for
Large-Scale SoC Designs

With a proven data model based on IP-XACT industry standard, Magillem Connectivity enables:

  • IP packaging for efficient handling of all aspects of system integration for connectivity and configurability
  • Automatic IPs instantiation and error-free connection process with solid API to access all the design data
  • Comprehensive HSI automation ensures better quality design and faster productivity.

The tool allows a significant jump in productivity, predictability with progress reporting, and portability of the design environment. For very large designs with thousands of instances, Magillem Connectivity streamlines the integration process decreasing design cycle time by up to 30%.

reduce integration process

Restructure for an Error-Free Design to Meet Power and Floorplanning Constraints

Eliminate painful, manual steps across the build flow and optimize time-consuming netlist for physical design with Magillem Connectivity. It delivers automated hierarchy manipulation capabilities with built-in checks ensuring high-quality generated design.

  • Separate RTL hierarchy and physical hierarchy, enabling powerful features including feedthrough connections for abutted floorplan and hard macros replication.
  • Rapid response to physical design requirements, reducing the process from weeks to 1-2 days.
  • Drastic improvement in development time and SoC quality through continuous integration flow.
IP-XACT design from RTL hierarchy to physical hierarchy

Error-Free System Map Generation

Synchronizing connectivity and memory map information with full integration of Magillem Registers and Magillem Connectivity:

  • Calculate and display the system map from the selected initiator.
  • Confirm that memory regions defined in the memory map can be reached (presence of a physical path).
  • Check that all the SW visible elements (registers or memory regions) in connected targets are present in the memory map.
generate error-free system map

Key Features

    • Project Management: Design navigation and data aggregation
    • Parameters Configuration: Hierarchical propagation or overriding
    • SoC Assembly: Bus i/f detection, rule-based connectivity, bus/signal split/tie/open, hierarchical connection, glue logic insertion, feedthrough
    • Hierarchy Manipulations: Move, merge, and flatten a physical/virtual hierarchy for RTL restructuring/partitioning
    • Platform Derivatives: With the incremental design, automatic update, and design diff and merge capability
    • Comprehensive Checkers: Catch errors as you enter the design information before running any simulation
    • Advanced Generation Capability: RTL Netlist generation, in addition to makefile scripts for an extensive range of EDA tools
    • Tool Integration: Tight link with the connectivity tool to generate a system address map when both tools are combined
import, capture, edit, update to check and validate to generate

NoC Integration Automated Flow

Automated flow to leverage SoC connectivity information:

  • Improved productivity with reduced process
  • Better quality with early errors detections thanks to the checkers

Learn about FlexNoC Interconnect IP

NoC integration automated flow

Magillem Connectivity Product Benefits

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True IP Reuse Methodology

For IPs and subsystems with vendor-independent IP packaging (IP-XACT based)

SoC assembly icon

Shorten and Streamline the Integration Process

Accelerating the connectivity through automation

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With a robust SoC build process that adapts safely and quickly to changes

single source of truth icon

Single Source
of Truth

Enabling consistency and interoperability between the design flow steps

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Correct by Construction

Thanks to the built-in checkers for higher quality designs

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Reduce Effort
and Rework

Automation ensures repeatability and eliminates human errors

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Technical Expertise

Reduce tedious and time-consuming tasks to focus on core business

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Higher quality design and shorter time to market

Product Options

Seamlessly Integrated Extensions to the Base Feature Set

architectural option

Architectural Option: UPF-Based Power Flow

  • Produce UPF script file
  • Produce diagram based on domain hierarchies
  • Powerful checks detecting early any issue or inconsistency between RTL and power intent
verification option

Verification Option: UVM Testbench Generation

  • Extend IP-XACT usage to Verification IP packaging and testbench assembly with consistency checkers
  • Enable scripting and automation, saving time for testing and debug of the DUT
  • Accelerate testbench generation with simulation script

Reliable and fast design capture: tedious tasks are hidden for the SoC integrator.

SoC Design Manager

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