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Magillem Packaging

An easy-to-use, scalable, and fully automated process to capture IP description in IP-XACT format

Magillem Packaging

Overview

Achieve design information consistency throughout the development lifecycle

Magillem Packaging uses a data model based on the IP_XACT industry standard to handle all aspects of system integration for connectivity, configurability, and system memory map. It enables true IP reuse methodology with an interoperable design flow for complex SoCs, including register management, IP capture, and SoC IP assembly.

With a nonintrusive, scalable, and automatic process for legacy and new IP that enables seamless IP client portfolio packaging, Magillem Packaging delivers both data accuracy and flexibility. It allows incremental or full packaging with IP-XACT compliance and data consistency that are ensured by construction and assessed with a built-in Magillem IP-XACT checkers suite.

Advantages

Comprehensive packaging for reuse in a single structured, standards-based format

Magillem Packaging includes configuration, implementation, and verification for incremental and full packaging with a proven methodology.

Correct by construction IP-XACT description

Improved quality without requiring any prerequisite IP-XACT expertise.

True IP reuse methodology

Ideal for IP and subsystems with vendor-independent IP packaging (IP-XACT based).

Single source-of-truth environment for system design

Enables multipurpose usage and helps ensure data consistency for design tasks and teams.

Magillem Packaging key features

IP-XACT 2022 support
HDL import: Verilog, SystemVerilog
Static elaboration support (with resolved configurations)
FileSet elaboration with full source file documentation
Bus interface automatic mapping of physical ports
Memory map intent capture
Catalog management
IP-XACT compliance checkers suite

Explore additional Magillem Packaging features, download the datasheet.

Full NoC integration for automated flow

Leverage SoC connectivity information:

Increase productivity with reduced process.
Improve quality with early error detection by checkers.

NoC Integration Automated Flow

Magillem Platform

Powerful comprehensive SoC integration automation

Category	Features	Magillem Packaging	Magillem Connectivity	Magillem Registers
IP-XACT Conversion	2009 to 2022
IP-XACT Conversion	2014 to 2022
Resource Management	Projects
	Catalogs
	Components
TGI	TGI API
HDL Import	Verilog/SystemVerilog support
HDL Import	View & FileSet elaboration
Bus Interface	Auto mapping
Rules Checkers	Design and component
	Memory and system map
	Configurable checker severity
Assembly	Rule-based connectivity
	Bus/signal split/tie/open/feedthrough
	Glue logic insertion
RTL Netlist Generation	Configurable header
	Keep parameter expressions
	Signals/netname/tie management
Hierarchical Manipulations	Merge, Flatten, Move operations
Hierarchical Manipulations	Parameter propagation
IP Update	Rename/resize/delete/merge
IP Update	User mapping rules definition
Diff and Merge	Accept/Reject any change
Diff and Merge	Conflict resolution wizard
Import Memory Map Description	SystemRDL support
	IP-XACT support
	Excel spreadsheets support
Generate HSI Outputs	RTL register bank (VHDL, Verilog, SystemVerilog)
	Customized C Header files
	UVM RAL files
	Documentation (Word, FrameMaker, HTML)
	SystemRDL description
	IP-XACT description

Partners

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Reliable and fast design capture: tedious tasks are hidden for the SoC integrator.

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