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Learn how FlexGen Smart NoC IP can optimize and advance your semiconductor design processes. Designed for automotive, data centers, and industrial electronics applications, it enables faster time-to-market and/or multiple design explorations for the most complex systems.

FlexGen smart NoC IP enables automated NoC design with reduced manual effort, shorter iteration cycles, and expert-level quality of results. SoC design teams can realize faster time-to-market, optimized power plus performance, reduced wire length, and improved overall design economics with FlexGen.

Ncore cache coherent NoC IP is scalable, configurable, and ISO 26262 certified. With Ncore, teams can derisk their SoC designs and deliver on their vision in record time, saving upwards of 50 years of engineering effort per project compared to manually generated solutions.

FlexNoC 5 physically aware network-on-chip IP incorporates physical constraint management across power, performance, and area (PPA). Get up to 5X faster physical convergence vs manual physical iterations and achieve PPA goals within schedule and budget constraints.

Phil Alsop, Editor of Silicon Semiconductor Magazine, discusses exciting developments with Arteris' Andy Nightingale including the launch of FlexGen and the immediate availability of the latest generation of Magillem Registers technology for SoC integration automation.

Andy Nightingale from Arteris talks about the demand for low-latency on-chip communication in increasingly complex devices, which can include chiplets, multiple networks on chip (NoCs), and the need for managing all of this with less power and using a simpler setup.