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Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications

This presentation covered the challenges and solutions of data–transport architectures for AI and ML in the context of embedded vision architectures and the implementation aspects for NoCs for RISC–V–based SoCs.

White Paper

Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product

Written by an ISO 26262 working group member who contributed to the new ISO 26262:2018 Part 11, this paper dispels myths about ISO 26262 certification and seeks to enhance the reader’s knowledge regarding all aspects of the ISO 26262 standard. This paper also discusses the standard’s applicability not only to electronic products, but also to the people and processes employed to create them.

White Paper

Re-Architecting SoCs for the AI Era

This paper defines AI, describe its applications, the problems it presents, and how chip designers can address those problems through new and holistic approaches to SoC and network on chip (NoC) design.It also describes challenges implementing AI functionality in automotive SoCs with ISO 26262 functional safety requirements.

White Paper

Using Synopsys Z01X to Accelerate the Fault Injection Campaign of a Fully Configurable IP

In this 4-page paper, created with the participation of Mobileye, you will learn how the world’s #1 vision-based automotive ADAS company uses Arteris FlexNoC interconnect IP to address demanding high bandwidth and low-latency requirements.

Presentation

Architecting the Future of Deep Learning Presentation

Learn about the history of artificial intelligence (AI), machine learning, (ML), and deep learning. Keynote presentation at the 2018 eSilicon “ASICs Unlock Deep Learning Innovation” seminar.

Presentation

Arm & Arteris AI and ISO 26262 Presentation

Arm & Arteris joint presentation from ICCAD China 2018 describes how new artificial (AI) and machine learning (ML) acceleration IP from Arm, like the Arm® NPU and Mali™ C71, can be implemented in ISO 26262-compliant automotive systems with the help of functional safety mechanisms in the Arteris FlexNoC and Ncore interconnects.

Presentation

Arm TechCon: Implementing ISO 26262 Compliant AI Systems-on-Chip with Arm and Arteris

Arm, Arteris, and Dream Chip Technologies joint presentation from Arm TechCon 2019 explains IP integration requirements for AI subsystems in ISO 26262-compliant chips. With an emphasis on techniques and safety mechanisms to enhance the diagnostic coverage of SoCs integrating an NPU and Safety Island. Topic areas include system design to comply with ISO 26262, system-level diagnostics, Network-on-Chip (NoC) safety mechanisms, subsystem isolation, and end-to-end error protection.

Presentation

Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip (SoCs)

Presented at IQPC Application of ISO 26262 2022 Conference, describes an approach that uses a hierarchal and modular library of safety components to describe failure modes, safety mechanism diagnostic coverage, and other functional safety metrics at a level that scales with the size and complexity of an SoC and enables reuse for the creation of SoC platform derivative chips, which is common in our industry.

Presentation

Challenges Adopting Fault Injection to Support Safety Analysis in Complex SoCs

Learn about fault simulator and EDA tools requirements; Using FMEA to create fault injection campaign; Guidelines/lesson learned for simulating different fault types; Analysis and documentation.

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Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications

CodaCache: Helping to Break the Memory Wall

Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product

Re-Architecting SoCs for the AI Era

Using Synopsys Z01X to Accelerate the Fault Injection Campaign of a Fully Configurable IP

Architecting the Future of Deep Learning Presentation

Arm & Arteris AI and ISO 26262 Presentation

Arm TechCon: Implementing ISO 26262 Compliant AI Systems-on-Chip with Arm and Arteris

Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip (SoCs)

Challenges Adopting Fault Injection to Support Safety Analysis in Complex SoCs

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