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Solution Brief

Accelerate and Optimize AI-Based SoC Designs with Arteris

Accelerate AI chip design with intelligent interconnect and system IP. Optimize performance, power, and area for AI-driven SoCs from data centers to edge devices. Enable faster innovation in generative AI, robotics, and autonomous systems with proven Arteris technology built for scalability and efficiency.
Optimizing Data Transport Architectures in RISC–V SoCs for AIML Applications
Video

Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications

This presentation covered the challenges and solutions of data–transport architectures for AI and ML in the context of embedded vision architectures and the implementation aspects for NoCs for RISC–V–based SoCs.
SemiEngineering Whiteboard Integration Challenges For RISC-V Designs
Video

Integration Challenges for RISC-V Designs

Modifying the source code allows for democratization of design, but it adds some hurdles for design teams.
SemiEngineering Whiteboard: Promises and Pitfalls of SoC Restructuring
Video

Promises and Pitfalls of SoC Restructuring

Learn about sidestepping data incompatibility issues in heterogeneous chip designs.
Scaling Performance In AI Systems
Video

Scaling Performance in AI Systems

AI designs face increasing challenges in balancing power, performance, and data throughput. Andy Nightingale from Arteris discusses how network-on-chip technology can help alleviate these bottlenecks and accelerate chip time-to-market.
CodaCache Helping to Break the Memory Wall
White Paper

CodaCache: Helping to Break the Memory Wall

This paper describes a novel configurable last level cache IP, CodaCache, that provides an easy-to-integrate solution giving system architects the capability to configure and adapt to their specific needs. Key technologies implemented in this IP are per-master way partitioning, scratchpad RAM allocation, AXI interfaces and functional safety mechanisms.
Fundamentals of Semiconductor ISO 26262 Certification People, Process and Product
White Paper

Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product

Written by an ISO 26262 working group member who contributed to the new ISO 26262:2018 Part 11, this paper dispels myths about ISO 26262 certification and seeks to enhance the reader’s knowledge regarding all aspects of the ISO 26262 standard. This paper also discusses the standard’s applicability not only to electronic products, but also to the people and processes employed to create them.
Re-Architecting SoCs for the AI Era
White Paper

Re-Architecting SoCs for the AI Era

This paper defines AI, describe its applications, the problems it presents, and how chip designers can address those problems through new and holistic approaches to SoC and network on chip (NoC) design.It also describes challenges implementing AI functionality in automotive SoCs with ISO 26262 functional safety requirements.
Using Synopsys Z01X to Accelerate the Fault Injection Campaign of a Fully Configurable IP
White Paper

Using Synopsys Z01X to Accelerate the Fault Injection Campaign of a Fully Configurable IP

In this 4-page paper, created with the participation of Mobileye, you will learn how the world’s #1 vision-based automotive ADAS company uses Arteris FlexNoC interconnect IP to address demanding high bandwidth and low-latency requirements.
Presentation

Architecting the Future of Deep Learning Presentation

Learn about the history of artificial intelligence (AI), machine learning, (ML), and deep learning. Keynote presentation at the 2018 eSilicon “ASICs Unlock Deep Learning Innovation” seminar.

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