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AI / Machine Learning (7) RISC-V Designs (6) Cybersecurity (5) ISO 26262 (4) Network-on-Chip IP (4) Traceability (4) FMEDA (3) Functional Safety (3) Hardware Security Assurance (3) IP-XACT (3) Magillem Connectivity (3) Multi-Die (3) FlexGen (2) Magillem Registers (2) Network-on-Chip (NoC) (2) Power Consumption (2) Automotive (1) CodaCache (1) FlexNoC (1) Hardware/Software Interface (HSI) (1) Magillem Packaging (1) Ncore (1) Power Management (1) Radix-S/M/ST (1) Routing Congestion (1) SystemC (1)
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Cover for PDF - 10 Key FlexGen Interconnect Advantages for Faster, Smarter SoC Design
Quick Reference Guides

10 Key FlexGen Interconnect Advantages for Faster, Smarter SoC Design

Explore how FlexGen automates NoC design to boost productivity, reduce latency and wirelength, and improve power efficiency in modern SoCs.
Considerations When Architecting Your Next SoC: NoC
Webinar

Considerations When Architecting  Your Next SoC: NoC

AI workloads are transforming SoC design, driving the need for faster data movement, lower latency, and higher energy efficiency. As AI and accelerated computing scale across heterogeneous architectures, the Network-on-Chip (NoC) has become the backbone that determines system performance, power efficiency, and overall scalability. In this SemiWiki-hosted webinar, Andy Nightingale, VP of Product Management and Marketing at Arteris, and Piyush Singh, Principal Digital SoC Architect at Aion Silicon, explore key considerations for architecting NoCs optimized for AI-driven designs. The discussion covers AI communication patterns, physically aware NoC topologies, multi-die integration and memory coherence challenges, performance simulation techniques, and NoC partitioning strategies to support scalable, power-aware AI systems from data center to edge.
Smart NoC Automation: Accelerating AI-Ready SoC Design in the Era of Chiplet
Video

Smart NoC Automation: Accelerating AI-Ready SoC Design in the Era of Chiplet

Explore how smart NoC generation can help optimize your NoC design processes by reducing iterations and bringing unprecedented quality of results.
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Solution Brief

Accelerate and Optimize AI-Based SoC Designs with Arteris

Optimize performance, power, and area for AI-driven SoCs from data centers to edge devices. Enable faster innovation in generative AI, physical AI, and autonomous systems with proven Arteris technology built for scalability, efficiency, and hardware assurance.
Podcast

SemiWiki: How NoC Tiling Capability is Changing the Game for AI Development with Andy Nightingale

Dan talks with Andy Nightingale from Arteris about new tiling capabilities and extended mesh topology support for network-on-chip IP products. They explore how these features address AI-driven chip design challenges.
FlexGen Smart NoC IP from Arteris Revolutionizes Complex SoC Designs -new
Video

FlexGen Smart NoC IP from Arteris Revolutionizes Complex SoC Designs

FlexGen smart NoC IP enables automated NoC design with reduced manual effort, shorter iteration cycles, and expert-level quality of results. SoC design teams can realize faster time-to-market, optimized power plus performance, reduced wire length, and improved overall design economics with FlexGen.
Guillaume accelerating timing closure
Video

Accelerating Timing Closure for Networks-on-Chip (NoCs) using Physical Awareness

Learn how to accelerate timing closure for Networks-on-Chip (NoCs) using physical awareness. Discover a flow and methodology to optimize NoC development and avoid timing surprises.
Chiplets: Opportunities and Challenges
Video

Chiplets: Opportunities and Challenges

Explore the challenges of chiplet interoperability and ecosystem collaboration and how leading companies are navigating this shift.
NoC-Centric System Performance for the Chiplet-Era with Platform Architect
Video

NoC-Centric System Performance for the Chiplet-Era with Platform Architect

Explore how Arteris NoC IPs and Platform Architect enhance system-level analysis for SoC designs in the chiplet era at the Synopsys Virtual Prototyping Day 2025.
Optimizing Data Transport Architectures in RISC–V SoCs for AIML Applications
Video

Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications

This presentation covered the challenges and solutions of data–transport architectures for AI and ML in the context of embedded vision architectures and the implementation aspects for NoCs for RISC–V–based SoCs.
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