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AI / Machine Learning (8) ISO 26262 (5) Functional Safety (4) Network-on-Chip IP (4) RISC-V Designs (4) Traceability (4) FMEDA (3) IP-XACT (3) Magillem Connectivity (3) Multi-Die (3) FlexGen (2) Magillem Registers (2) Network-on-Chip (NoC) (2) Power Consumption (2) Automotive (1) CodaCache (1) Cybersecurity (1) FlexNoC (1) Hardware Security Assurance (1) Hardware/Software Interface (HSI) (1) Magillem Packaging (1) Ncore (1) Power Management (1) Radix-S/M/ST (1) Routing Congestion (1) SystemC (1)
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Solution Brief

Accelerate and Optimize AI-Based SoC Designs with Arteris

Optimize performance, power, and area for AI-driven SoCs from data centers to edge devices. Enable faster innovation in generative AI, physical AI, and autonomous systems with proven Arteris technology built for scalability, efficiency, and hardware assurance.
Podcast

SemiWiki: How NoC Tiling Capability is Changing the Game for AI Development with Andy Nightingale

Dan talks with Andy Nightingale from Arteris about new tiling capabilities and extended mesh topology support for network-on-chip IP products. They explore how these features address AI-driven chip design challenges.
Guillaume accelerating timing closure
Video

Accelerating Timing Closure for Networks-on-Chip (NoCs) using Physical Awareness

Learn how to accelerate timing closure for Networks-on-Chip (NoCs) using physical awareness. Discover a flow and methodology to optimize NoC development and avoid timing surprises.
Chiplets: Opportunities and Challenges
Video

Chiplets: Opportunities and Challenges

Explore the challenges of chiplet interoperability and ecosystem collaboration and how leading companies are navigating this shift.
NoC-Centric System Performance for the Chiplet-Era with Platform Architect
Video

NoC-Centric System Performance for the Chiplet-Era with Platform Architect

Explore how Arteris NoC IPs and Platform Architect enhance system-level analysis for SoC designs in the chiplet era at the Synopsys Virtual Prototyping Day 2025.
Optimizing Data Transport Architectures in RISC–V SoCs for AIML Applications
Video

Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications

This presentation covered the challenges and solutions of data–transport architectures for AI and ML in the context of embedded vision architectures and the implementation aspects for NoCs for RISC–V–based SoCs.
SemiEngineering Whiteboard Integration Challenges For RISC-V Designs
Video

Integration Challenges for RISC-V Designs

Modifying the source code allows for democratization of design, but it adds some hurdles for design teams.
SemiEngineering Whiteboard: Promises and Pitfalls of SoC Restructuring
Video

Promises and Pitfalls of SoC Restructuring

Learn about sidestepping data incompatibility issues in heterogeneous chip designs.
Scaling Performance In AI Systems
Video

Scaling Performance in AI Systems

AI designs face increasing challenges in balancing power, performance, and data throughput. Andy Nightingale from Arteris discusses how network-on-chip technology can help alleviate these bottlenecks and accelerate chip time-to-market.
Power Dissipation of the Network-on-Chip in a System-on-Chip for MPEG-4 Video Encoding
White Paper

Power Dissipation of the Network-on-Chip in a System-on-Chip for MPEG-4 Video Encoding

An oldie but a goodie: Explains power benefits of NoC technology by characterizing a multi-processor system-on-chip (MPSoC) for MPEG4, AVC/H.264 encoding. Explains NoC power model used to analyze power consumption and dissipation.
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