Contact Us
Generic selectors
Exact matches only
Search in title
Search in content
Post Type Selectors

Resources Search

background-element-24

Sort & Filter

Type
Resources catergories filter
Resources Type Filter
Tags filter
Show More
Year filter
Show More
Latest
Oldest
A-Z
Z-A
Filter by Product
Filter by Solution
110 Results
Sort & Filter
AI solution brief thumbnail
Solution Brief

Accelerate and Optimize AI-Based SoC Designs with Arteris

Accelerate AI chip design with intelligent interconnect and system IP. Optimize performance, power, and area for AI-driven SoCs from data centers to edge devices. Enable faster innovation in generative AI, robotics, and autonomous systems with proven Arteris technology built for scalability and efficiency.
Podcast

SemiWiki: How NoC Tiling Capability is Changing the Game for AI Development with Andy Nightingale

Dan talks with Andy Nightingale from Arteris about new tiling capabilities and extended mesh topology support for network-on-chip IP products. They explore how these features address AI-driven chip design challenges.
Guillaume accelerating timing closure
Video

Accelerating Timing Closure for Networks-on-Chip (NoCs) using Physical Awareness

Learn how to accelerate timing closure for Networks-on-Chip (NoCs) using physical awareness. Discover a flow and methodology to optimize NoC development and avoid timing surprises.
Chiplets: Opportunities and Challenges
Video

Chiplets: Opportunities and Challenges

Explore the challenges of chiplet interoperability and ecosystem collaboration and how leading companies are navigating this shift.
NoC-Centric System Performance for the Chiplet-Era with Platform Architect
Video

NoC-Centric System Performance for the Chiplet-Era with Platform Architect

Explore how Arteris NoC IPs and Platform Architect enhance system-level analysis for SoC designs in the chiplet era at the Synopsys Virtual Prototyping Day 2025.
Optimizing Data Transport Architectures in RISC–V SoCs for AIML Applications
Video

Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications

This presentation covered the challenges and solutions of data–transport architectures for AI and ML in the context of embedded vision architectures and the implementation aspects for NoCs for RISC–V–based SoCs.
SemiEngineering Whiteboard Integration Challenges For RISC-V Designs
Video

Integration Challenges for RISC-V Designs

Modifying the source code allows for democratization of design, but it adds some hurdles for design teams.
SemiEngineering Whiteboard: Promises and Pitfalls of SoC Restructuring
Video

Promises and Pitfalls of SoC Restructuring

Learn about sidestepping data incompatibility issues in heterogeneous chip designs.
Scaling Performance In AI Systems
Video

Scaling Performance in AI Systems

AI designs face increasing challenges in balancing power, performance, and data throughput. Andy Nightingale from Arteris discusses how network-on-chip technology can help alleviate these bottlenecks and accelerate chip time-to-market.
Application Driven Network-on Chip Architecture Exploration & Refinement for a Complex SoC
White Paper

Application Driven Network-on Chip Architecture Exploration & Refinement for a Complex SoC

Peer-reviewed technical journal article from Springer’s “Design Automation for Embedded Systems Journal.” Summarizes the various features a NoC is required to implement to be integrated in modern SoCs. Describes a top-down approach, based on the progressive refinement of the NoC description from its functional specification (Sect. 4) to its verification (Sect. 8).

No results found

Make sure all words are spelled correctly. Try different, more general, or fewer keywords.

Call to Action
Popup Overlay