Accelerating Timing Closure for Networks-on-Chip (NoCs) using Physical Awareness
Learn how to accelerate timing closure for Networks-on-Chip (NoCs) using physical awareness. Discover a flow and methodology to optimize NoC development and avoid timing surprises.
Video
Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications
This presentation covered the challenges and solutions of data–transport architectures for AI and ML in the context of embedded vision architectures and the implementation aspects for NoCs for RISC–V–based SoCs.
White Paper
Application Driven Network-on Chip Architecture Exploration & Refinement for a Complex SoC
Peer-reviewed technical journal article from Springer’s “Design Automation for Embedded Systems Journal.” Summarizes the various features a NoC is required to implement to be integrated in modern SoCs. Describes a top-down approach, based on the progressive refinement of the NoC description from its functional specification (Sect. 4) to its verification (Sect. 8).
Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product
Written by an ISO 26262 working group member who contributed to the new ISO 26262:2018 Part 11, this paper dispels myths about ISO 26262 certification and seeks to enhance the reader’s knowledge regarding all aspects of the ISO 26262 standard. This paper also discusses the standard’s applicability not only to electronic products, but also to the people and processes employed to create them.
How to Efficiently Achieve ASIL-D Compliance Using NoC Technology
A closer look at ASIL-D compliance options for on-chip interconnects and NoCs, including redundancy, path diversity and error correction codes (ECC) is required to fully optimize an on-chip network to meet rapidly evolving technology and customer demands.
Optimizing Enterprise-Class SSD Host Controller Design with Arteris FlexNoC Network-On-Chip Interconnect IP
Enterprise SSD Endurance & Data Protection technical paper that explains how the leading enterprise SSD controller design teams are using network-on-chip (NoC) interconnect technology to optimize their designs for power consumption and performance while increasing reliability and availability.
Power Dissipation of the Network-on-Chip in a System-on-Chip for MPEG-4 Video Encoding
An oldie but a goodie: Explains power benefits of NoC technology by characterizing a multi-processor system-on-chip (MPSoC) for MPEG4, AVC/H.264 encoding. Explains NoC power model used to analyze power consumption and dissipation.
This paper defines AI, describe its applications, the problems it presents, and how chip designers can address those problems through new and holistic approaches to SoC and network on chip (NoC) design.It also describes challenges implementing AI functionality in automotive SoCs with ISO 26262 functional safety requirements.
The congestion of wires in the place and route (P&R) stage of chip design poses an increasingly significant challenge to creating low cost, high performance chip designs. This paper introduces packet based network-on-chip as a means of enabling configuration link widths, shows experimental results, and describes other benefits of packet-based interconnect networks.
Scalability – A Looming Problem in Safety Analysis
Misbehavior in the electronics can lead to accidents, even fatalities. This paper describes how ISO 26262 standard and in particular the Failure Modes, Effects and Diagnostic Analysis (FMEDA) can be leveraged to address this real concern.
