Resources Search

Video

Magillem Registers – Automate the Hardware/Software Interface for Fast Chip Design

Magillem Registers is a comprehensive register design and management technology that accurately automates the hardware/software interface (HSI) to quickly develop chips and chiplets ranging from IoT devices to complex AI datacenter multi-die SoCs.

Video

Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications

This presentation covered the challenges and solutions of data–transport architectures for AI and ML in the context of embedded vision architectures and the implementation aspects for NoCs for RISC–V–based SoCs.

White Paper

A Configurable Test Infrastructure using a Mixed-Language and Mixed-Level IP Integration IP-XACT Flow

This paper written with NXP describes an efficient integration flow for mixed-language and mixed-abstraction level IPs through IP-XACT flow automation.

White Paper

A SystemC Extension for Enabling Tighter Integration of IP-XACT Platforms with Virtual Prototypes

This paper describes a configurable SystemC extension that simplifies the syntax for expressing register and bit field accesses and enables automation of virtual platform and hardware-software interface (HSI) development.

White Paper

AMS System-Level Verification and Validation using UVM in SystemC and SystemC-AMS: Automotive Use Cases

This 12-page paper published in the peer-reviewed IEEE Design & Test journal explains how Universal Verification Methodology (UVM), initially developed for digital systems, can be extended to analog and mixed signal systems with the help if IP-XACT-based IP packaging and design flow automation.

White Paper

Building a Portable Stimulus Flow Based on Magillem IP-XACT Packaging

This paper written by Nokia and Mentor Siemens describes an efficient integration flow using Portable Stimulus and IP-XACT flow automation.

White Paper

Generation of UVM Compliant Test Benches for Automotive Systems using IP-XACT with UVM-SystemC and SystemC AMS

This paper presents a methodology and flow to automate the test bench creation for automotive heterogeneous HW/SW systems, using SystemC, SystemC-AMS and IP-XACT.

White Paper

HW / SW Interface Generation Flow Based on Abstract Models of System Applications and Hardware Architectures

This paper presents a code generation flow to deploy system applications over hardware architectures based on abstract descriptions.

White Paper

Scalability – A Looming Problem in Safety Analysis

Misbehavior in the electronics can lead to accidents, even fatalities. This paper describes how ISO 26262 standard and in particular the Failure Modes, Effects and Diagnostic Analysis (FMEDA) can be leveraged to address this real concern.

Presentation

Architecting the Future of Deep Learning Presentation

Learn about the history of artificial intelligence (AI), machine learning, (ML), and deep learning. Keynote presentation at the 2018 eSilicon “ASICs Unlock Deep Learning Innovation” seminar.

Resources Search

Sort & Filter

No results found

Headquarters