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Cover for PDF - 7 Ways Magillem Registers Streamlines Hardware-Software Interface Design
Quick Reference Guides

7 Ways Magillem Registers Streamlines Hardware-Software Interface Design

Navigate the complexity of managing registers and maintaining tight alignment between hardware and software teams, avoiding costly delays and redesigns.
Presentation

Will it Blend? – Verifying the Hardware / Software Interface of Complex SoCs

This presentation highlights how Arteris SoC integration automation technologies streamline the blend of hardware, software, and verification components including VHDL, SystemVerilog, UPF, IP-XACT, and UVM to boost productivity and enable first-time silicon success.
AI solution brief thumbnail
Solution Brief

Accelerate and Optimize AI-Based SoC Designs with Arteris

Optimize performance, power, and area for AI-driven SoCs from data centers to edge devices. Enable faster innovation in generative AI, physical AI, and autonomous systems with proven Arteris technology built for scalability, efficiency, and hardware assurance.
Magillem Registers - Automate the HardwareSoftware Interface for Fast Chip Design
Video

Magillem Registers – Automate the Hardware/Software Interface for Fast Chip Design

Magillem Registers is a comprehensive register design and management technology that accurately automates the hardware/software interface (HSI) to quickly develop chips and chiplets ranging from IoT devices to complex AI datacenter multi-die SoCs.
Chiplets: Opportunities and Challenges
Video

Chiplets: Opportunities and Challenges

Explore the challenges of chiplet interoperability and ecosystem collaboration and how leading companies are navigating this shift.
Optimizing Data Transport Architectures in RISC–V SoCs for AIML Applications
Video

Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications

This presentation covered the challenges and solutions of data–transport architectures for AI and ML in the context of embedded vision architectures and the implementation aspects for NoCs for RISC–V–based SoCs.
SemiEngineering Whiteboard Integration Challenges For RISC-V Designs
Video

Integration Challenges for RISC-V Designs

Modifying the source code allows for democratization of design, but it adds some hurdles for design teams.
SemiEngineering Whiteboard: Promises and Pitfalls of SoC Restructuring
Video

Promises and Pitfalls of SoC Restructuring

Learn about sidestepping data incompatibility issues in heterogeneous chip designs.
Configurable Test Infra with Mixed-Language & IP-XACT Integration Flow
White Paper

A Configurable Test Infrastructure using a Mixed-Language and Mixed-Level IP Integration IP-XACT Flow

This paper written with NXP describes an efficient integration flow for mixed-language and mixed-abstraction level IPs through IP-XACT flow automation.
AMS System Verification with UVM in SystemC & SystemC-AMS for Autos
White Paper

AMS System-Level Verification and Validation using UVM in SystemC and SystemC-AMS: Automotive Use Cases

This 12-page paper published in the peer-reviewed IEEE Design & Test journal explains how Universal Verification Methodology (UVM), initially developed for digital systems, can be extended to analog and mixed signal systems with the help if IP-XACT-based IP packaging and design flow automation.

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