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Smart NoC Automation: Accelerating AI-Ready SoC Design in the Era of Chiplet
Video

Smart NoC Automation: Accelerating AI-Ready SoC Design in the Era of Chiplet

Explore how smart NoC generation can help optimize your NoC design processes by reducing iterations and bringing unprecedented quality of results.
Magillem Registers - Automate the HardwareSoftware Interface for Fast Chip Design
Video

Magillem Registers – Automate the Hardware/Software Interface for Fast Chip Design

Magillem Registers is a comprehensive register design and management technology that accurately automates the hardware/software interface (HSI) to quickly develop chips and chiplets ranging from IoT devices to complex AI datacenter multi-die SoCs.
Guillaume accelerating timing closure
Video

Accelerating Timing Closure for Networks-on-Chip (NoCs) using Physical Awareness

Learn how to accelerate timing closure for Networks-on-Chip (NoCs) using physical awareness. Discover a flow and methodology to optimize NoC development and avoid timing surprises.
Optimizing Data Transport Architectures in RISC–V SoCs for AIML Applications
Video

Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications

This presentation covered the challenges and solutions of data–transport architectures for AI and ML in the context of embedded vision architectures and the implementation aspects for NoCs for RISC–V–based SoCs.
Accelerating IP Reuse
Video

Accelerating IP Reuse

Semiconductors now rely on up to 1,000 third-party IPs in complex SoCs, requiring seamless integration. Insaf Meliane of Arteris discusses with Semiconductor Engineering how the latest IP-XACT version simplifies automation, abstraction, and system integration.
SemiEngineering Cache Coherency in Heterogeneous Systems
Video

Cache Coherency in Heterogeneous Systems

Why maintaining flexibility in coherency is essential in heterogeneous designs. A video discussion with Semiconductor Engineering’s Ed Sperling.
SemiEngineering Whiteboard Integration Challenges For RISC-V Designs
Video

Integration Challenges for RISC-V Designs

Modifying the source code allows for democratization of design, but it adds some hurdles for design teams.
SemiEngineering Whiteboard: Promises and Pitfalls of SoC Restructuring
Video

Promises and Pitfalls of SoC Restructuring

Learn about sidestepping data incompatibility issues in heterogeneous chip designs.
Scaling Performance In AI Systems
Video

Scaling Performance in AI Systems

AI designs face increasing challenges in balancing power, performance, and data throughput. Andy Nightingale from Arteris discusses how network-on-chip technology can help alleviate these bottlenecks and accelerate chip time-to-market.
Re-Architecting SoCs for the AI Era
White Paper

Re-Architecting SoCs for the AI Era

This paper defines AI, describe its applications, the problems it presents, and how chip designers can address those problems through new and holistic approaches to SoC and network on chip (NoC) design.It also describes challenges implementing AI functionality in automotive SoCs with ISO 26262 functional safety requirements.

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