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Presentation

Will it Blend? – Verifying the Hardware / Software Interface of Complex SoCs

This presentation highlights how Arteris SoC integration automation technologies streamline the blend of hardware, software, and verification components including VHDL, SystemVerilog, UPF, IP-XACT, and UVM to boost productivity and enable first-time silicon success.
Presentation

Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip (SoCs)

Presented at IQPC Application of ISO 26262 2022 Conference, describes an approach that uses a hierarchal and modular library of safety components to describe failure modes, safety mechanism diagnostic coverage, and other functional safety metrics at a level that scales with the size and complexity of an SoC and enables reuse for the creation of SoC platform derivative chips, which is common in our industry.
Presentation

Building Better IP with RTL Architect NoC IP Physical Exploration

Voted one of the “Top Ten Best Presentations” at SNUG Silicon Valley 2023, this presentation discusses the importance of NoCs and their impact on timing analysis and power consumption. It introduces a flow and methodology that utilizes RTL-based estimation of timing and power consumption using RTL Architect in conjunction with Arteris’ FlexNoC 5 and Ncore NoC development frameworks. FlexNoC 5 facilitates up to 5X faster physical convergence of the back-end physical design time and effort.
Presentation

Efficient Scaling of AI Accelerators Using NoC Tiling

Learn about the benefits of using NoC tiling in AI accelerators, seamless data management with NoC solutions and real-world applications for AI vision.
Presentation

FMEDA Automation for Scalability and Reuse in Complex Systems on Chips (SoCs)

Failure modes, effects, and diagnostic analysis (FMEDA) for sophisticated chips with hundreds of IP blocks are fraught with complexity and opportunities for systematic errors. This presentation will describe an approach that uses a hierarchal and modular library of safety components to describe failure modes, safety mechanism diagnostic coverage, and other functional safety metrics.
Presentation

Is the Missing Safety Ingredient in Automotive AI Traceability?

Presented at The Linley Spring Processor Conference 2022, describes the importance of traceability as it applies to managing SoC requirements and customer deliverables whilst also shortening the path to functional safety certification including ISO 26262.
Presentation

Modernizing the Hardware / Software Interface – Life Beyond Spreadsheets

How to bring your SoC register design into the 21st Century. The presentation from DVCon US 2025 discusses the current industry challenges and how Magillem Registers has the features and flexibility to speed up the development of the largest and most complex designs.
Presentation

Safety Considerations for Network-on-Chip (NoC) Development

This presentation illustrates functional safety challenges in system design and adherence to the ISO 26262 standard for automotive electronics. It highlights Network-on-Chip (NoC) safety mechanisms, including timeouts, IP Block isolation, and end-to-end interface protection.
Presentation

The Role of Networks-on-Chips Enabling AI/ML Silicon and Systems

Discover how networks-on-chips (NoCs) are revolutionizing AI/ML across sensors, edge devices, and data centers. This video presentation explores how NoCs enable rapid data movement, seamless component integration, and efficient chip-to-chip communication, paving the way for a new era of AI-powered devices.
Presentation

Tiled Approach to System Scaling

Today’s large-scale SoCs such as AI accelerators often deploy regular repeating arrays of processor elements. See how tiling accelerates physical design by enabling re-use of hardened physical blocks in addition to logical elements.
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