Connecting and securing RISC-V designs with Arteris
RISC-V is enabling a new era of highly customizable SoCs, but this flexibility also introduces significant challenges in connectivity, integration, and security. Modern designs must efficiently connect hundreds of heterogeneous IP blocks, manage diverse protocols and coherency models, and ensure robust protection against increasingly sophisticated hardware threats.
In this session, we will show how Arteris addresses these challenges with a comprehensive system IP approach. At the core is silicon-proven Network-on-Chip (NoC) technology, which provides a scalable, physically aware communication backbone to unify protocols, optimize data movement, and enable predictable performance across complex RISC-V SoCs. Complementing this, Arteris SoC integration automation solutions streamline IP assembly, automate connectivity, and significantly reduce design risk, accelerating time-to-market while improving overall system quality.
Beyond connectivity and integration, security is becoming a first-class design requirement. We will introduce Arteris’ Radix hardware security assurance solutions, which enable early detection and mitigation of vulnerabilities through simulation, emulation, and static analysis across the SoC design flow. Together, these capabilities enable engineering teams to build not only high-performance RISC-V systems but also secure, trustworthy silicon.
