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Chiplets 101: An Arteris Guide to Multi-Die Architecture

View our guide to chiplets and multi-die architecture, explaining interconnect, data movement, memory, and design strategies for scalable high-performance SoC systems.

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Semiconductor Engineering: Facilitating Complex SoC Design Through Automation And Integration

Automation and integration tools unify IP, connectivity, and software design, enabling scalable, efficient SoC development and reducing manual complexity. Learn more about how unified system definitions, automated interconnect generation, and coordinated design flows improve performance, productivity, and time-to-market in the

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Arteris Celebrates One Year in Poland with New and Expanded Partnerships

Arteris marked the first anniversary of its Krakow engineering hub, highlighting a year of growth, innovation, and deeper integration into Europe’s semiconductor ecosystem. The milestone included expanded partnerships with leading Polish universities, reinforcing collaboration in research, education, and talent development.

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Design & Reuse: Topology and Data Movement in Multi-Die Design

This article explores how multi-die design shifts the primary challenge from scaling silicon to managing data movement and system integration across chiplets. It highlights the critical role of NoC topology in controlling traffic, latency, and coherency between dies, as well

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The 5 Biggest Challenges in Modern SoC Design (And How to Solve Them)

Modern system-on-chip (SoC) performance is no longer compute-bound. It is increasingly data-movement–bound and wire-limited.

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Arteris × XuanTie: The “Data Highway” for High-Performance RISC-V SoCs

Arteris and XuanTie have formed a deep partnership, leveraging the Ncore cache-coherent NoC IP as the core to build a "data highway" for high-performance RISC-V SoCs. Ncore paired with the XuanTie C930 delivers 30 GB/s/GHz bandwidth and 110-cycle latency, supporting

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Building Secure Chips: Why Hardware Security Assurance Is Now Essential

Hardware security is no longer optional. At DAC 2025, industry leaders share how teams are shifting from traditional verification to measurable security assurance without breaking budgets or schedules. Learn what’s changing, why it matters, and how to build trust into

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Semiconductor Engineering: Importance Of Hardware Security Verification In Pre-Silicon Design

Security in modern semiconductor design must be built in from the start, not validated after the fact. This article explains how pre-silicon hardware security verification relies on two key pillars — functional verification to ensure security features behave correctly, and

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EDN: Chiplet innovation isn’t waiting for perfect standards

As monolithic SoCs reach their limits, chiplets offer a more scalable and cost-effective path forward. Despite incomplete standards, companies are moving ahead using modular design and flexible interconnects, with Arteris highlighting the role of NoC IP and automation in enabling

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EDN: Last-level cache has become a critical SoC design element

As AI-driven SoCs integrate increasingly heterogeneous compute engines, last-level cache (LLC) has become a critical architectural element for balancing performance, power, and determinism. Positioned between on-chip subsystems and external memory, LLC reduces latency and off-chip traffic but only when carefully

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