Home » Search Results

Search Results

1024 Results

Filter

EDN: AI workloads demand smarter SoC interconnect design

This EDN article explains how AI workloads are pushing traditional SoC interconnect design beyond practical limits, making intelligent automation essential. Physically aware NoC algorithms optimize topology, power, latency, and timing closure, enabling scalable AI SoCs from data centers to the

Learn more about post

2026 Predictions: System-Level Design, AI-Native Workflows, and the Rise of Multi-Die Compute Fabrics

Explore 2026 semiconductor predictions as AI accelerates system-level design, multi-die compute fabrics, chiplets, 2.5D/3D integration, and AI-native architecture workflows reshape how advanced systems are built and verified.

Learn more about post

Advancing Europe’s Automotive Chiplet Vision: Arteris Joins CHASSIS to Accelerate Software-Defined Mobility

Arteris joins CHASSIS, Europe’s open automotive chiplet initiative with advanced NoC and multi-die interconnect technology that accelerates software-defined mobility.

Learn more about post

Semiconductor Engineering: A Golden Source As The Single Source Of Truth In HSI

Maintaining alignment between hardware and software is one of the biggest challenges in complex SoC design. A single, machine-readable golden source keeps every element from RTL to drivers and documentation perfectly synchronized. Learn how Arteris’ Magillem Platform makes this possible

Learn more about post

Power Electronics Magazine: How Network-on-Chip Architectures Are Powering the Future of Microcontroller Design

Network-on-Chip (NoC) technology is redefining how microcontrollers (MCUs) handle performance, power efficiency, and scalability. As MCUs take on more complex, AI-driven, and safety-critical tasks, NoC architectures provide the structured, high-speed interconnects needed to keep pace. Learn more about how Arteris

Learn more about post

Semiconductor Engineering: Efficiency Defines The Future Of Data Movement

As AI workloads expand and chiplet architectures evolve, data movement now consumes more energy than computation itself. Achieving higher performance within fixed power budgets demands efficient, intelligent interconnects and automation across multi-die SoC designs. Learn more in the article.

Learn more about post

EE Times: A Guide to Building Chiplets Today While Shaping Tomorrow’s Standards

Chiplet standards like UCIe, AIB, and BoW are still evolving, but design teams can start building with chiplets today by adopting packaging automation, structured IP metadata, and scalable interconnect fabrics that enable flexibility and future-proof integration. Learn how to design

Learn more about post

EDN: A Logically Correct SoC Design Isn’t an Optimized Design

Automation in SoC design is evolving beyond correctness toward true optimization. Just as modern GPS systems account for real-world traffic, AI-driven, physically aware automation for NoC design minimizes wire length, manages congestion, and adapts dynamically to design changes — closing

Learn more about post

Semiconductor Engineering: The Future Of SoC Design Is Data Movement

The semiconductor industry is shifting from focusing on raw compute to tackling the growing challenge of data movement in complex SoCs. With advances in chiplets, high-bandwidth memory, CXL fabrics, and automotive zonal architectures, predictable performance now depends on layered, automated,

Learn more about post

Electronic Design: Speeding the Process of Building IPs, Chiplets, and SoCs

Designing modern SoCs and multi-die systems requires faster integration of thousands of IP blocks and chiplets while minimizing errors. Structured metadata standards like IP-XACT, combined with automation, are transforming this process by ensuring consistency, tool interoperability, and accurate hardware/software alignment

Learn more about post

No results found

Make sure all words are spelled correctly. Try different, more general, or fewer keywords.

Popup Overlay