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I’ve received a lot of feedback on the “Interchip Connectivity: HSIC, UniPro, HSI, C2C, LLI…oh my!” article I wrote last year and I thank everyone for their feedback!

It may seem strange to link two interchip interface standards to the future of 3D integrated circuits, but please bear with me for a few minutes. I hope to prove that the learning from today will impact how we design

Samsung’s announcement that it is investing a company-record $42B in 2012 for technology development came as a bit of a shock to many in the financial and technology press. The size of this investment dwarfs that of any other company

Two new options for interchip connectivity are available today that enable sharing a DRAM memory between two chips for data and programs. These standards, called MIPI Low Latency Interface (MIPI LLI) and Chip-to-Chip (C2C), are primarily targeted at mobile phones,

Gartner analyst Jim Tully’s assessment that network on chip (NoC) technology will be “mainstream” in two to five years is an acknowledgement of the technical and commercial success NoC interconnect IP has had in the consumer electronics system on chip

When I speak to semiconductor product managers, directors and VPs, one of the questions I often ask is, “How much does it cost you if your chip is one month late?”

As featured in: I’ve been hearing the term “IP subsystem” lately, and it seems to be the latest newfangled buzz word in the SoC semiconductor and IP industry, second only to “virtualization.” Much of the context for this growing interest

Provides compatibility with ARM AMBA 4 CCI-400 and Cortex-A15 cores while reducing routing congestion, easing timing closure and increasing performance

Today in the IP and EDA business, I hear “knock” all the time, except people mean “NoC.” It seems everybody wants a NoC, or wants to offer you a NoC. I’m here to tell you that NoC is not a

TI has placed extensive information on their new OMAP5430 and OMAP5432 processors on their web page.