SoC & Hardware / Software Interface (HSI) Development

For IP and VIP Providers

For IP Providers

  • IP-XACT packages correct by construction: The standard is complex, unfamiliar to many. Get it right the first time; sign it off with our checkers
  • Add control and status registers (CSR) to legacy IP: Build custom register banks to provide software control, status checks to any IP
  • Supports full and incremental packaging of both IP and VIP
  • Comprehensive view, configurability support: Package Verilog, System Verilog UVM, VHDL, SystemC views, clocking data, interface typing, register maps, configuration options
  • Supports SystemVerilog UVM VIP code generation from IP-XACT model

For IC Integrators

For IC Integrators

  • Instantiate IPs, connect your SoC: Complete tooling to instantiate, configure packaged IP into a design and create all connectivity
  • Hybrid platform support: Mix AMS, SystemC, VHDL and Verilog IPs
  • Build virtual prototypes or implementation-ready designs: Build SystemC or RTL views as needed
  • Restructure hierarchy at will: Repurpose legacy design structure, adapt to power and floor-planning constraints
  • Built-in static checks: Find and fix basic problems in real-time
  • Verification support: Expedite time-to-first-test with SystemVerilog UVM VIP modeling in IP-XACT, UVM environment creation and maintenance, and testbench assembly and generation

For HSI Developers

For Hardware / Software Interface (HSI) Developers

  • Automatic memory map generation: Generates SoC memory map from configured IP register maps and interconnect memory maps
  • Generate software headers: Symbolic IP, register, bitfield names and offsets, access macros, sequence macros. Always consistent, complete
  • Static checking: Provides comprehensive consistency checks, e.g., memory spaces for different IPs should not overlap
  • UVM verification templates: The tool generates these templates automatically, in support of comprehensive dynamic register access checking and supports UVM RAL

Automate, and focus on what you do best.

Design Process Unification

Design Process Unification

One standard platform for all product designs, directly integrating with most commercial IP releases. Handles IP configuration and instantiation, connectivity, flexible hierarchy management, interfaces to verification and implementation. Automatically builds, checks consistency for memory maps. A single source of truth for hardware verification at virtual prototype and RTL abstractions, and for the hardware / software interface.

Leverage Differentation

Leverage Differentiation

Standards don’t mean you have to give up technical advantages in clever design techniques. Customization through the API allows you to retain those advantages and ensure they can be shared across the organization if beneficial, unlike many scripts siloed within individual teams.