Microcontroller solutions for modern architectures
Enable next-generation microcontrollers with network-on-chip technology designed around efficiency, scalability, and safety.
Overview
Scalable solutions for next-gen MCUs
Modern microcontrollers are taking on more complex control, connectivity, safety, and edge-intelligence workloads. Arteris helps MCU design teams scale data movement, integration, and verification while protecting the MCU priorities of cost, power, determinism, and implementation simplicity.
The Arteris MCU solution portfolio helps architecture teams move beyond bus and crossbar limits without giving up the power, cost, safety, and schedule discipline that defines successful microcontroller programs. FlexGen®, FlexNoC®, FlexWay®, CodaCache®, Ncore™, Radix, and Magillem® each address a different pressure point: scalable data movement, memory locality, hardware security assurance, functional safety, and repeatable integration.
| Portfolio item | How it helps MCU designs |
|---|---|
| Non-Coherent NoC IP | Highly configurable Arteris network-on-chip fabric technology brings physical awareness to help accelerate timing closure, reduce wires, and increase SoC performance. |
| CodaCache | Keeps reused data close to compute so edge AI, signal processing, and sensor workloads can reduce memory latency and off-chip access power. |
| Ncore | Adds coherent NoC capability for MCU platforms that need shared-memory coherency across application-class cores, accelerators, or heterogeneous compute clusters. |
| Radix | Adds pre-silicon hardware security assurance so connected and regulated MCUs can identify vulnerabilities before tape-out. |
| Magillem | Turns IP packaging, connectivity, register maps, and documentation into a consistent automation flow instead of a late-stage integration scramble. |
Advantages
Built for the demands of modern MCU design
Optimized PPA
FlexGen, FlexNoC, and FlexWay help improve power, performance, and area outcomes for advanced MCU-class use cases. CodaCache can be paired with these interconnects to support memory bandwidth and access needs, including AI/ML-oriented workloads. Ncore addresses coherent CPU clusters separately, combining coherent interconnect with built-in cache capability to support predictable shared-memory performance.
Safety
Arteris system IP supports ISO 26262-oriented design, verification, and documentation workflows, including safety-compliant NoC development for automotive and other mission-critical systems across aerospace,defense, and industrial applications.
Security assurance
Cycuity adds hardware security assurance and verification coverage for MCU programs that need stronger cybersecurity evidence.
Simplified MCU integration
Magillem tools automate chip integration workflows, including IP-XACT-based collaboration, to help shorten MCU development cycles and reduce handoff friction.
Ecosystem
Collaboration around the globe
Arteris collaborates with semiconductor vendors and IoT solution providers around the world to support optimized MCU interconnect IP solutions.
Standards focused for interoperability
MCU teams can build around established interface and safety ecosystems, including AMBA protocols, ISO 26262-oriented workflows, and interoperability with controller and PHY interface partners.
Advanced Microcontroller Bus Architecture reference for interoperability.
Peripheral Component Interconnect Express ecosystem reference.
Alphawave Semi, Blue Cheetah, Cadence, Innosilicon, Synopsys, and others are referenced for NoC-to-controller/PHY interface alignment.
FlexWay 5 Core Interconnect IP: A non-coherent, cost-effective interconnect solution
FlexWay gives entry-level consumer electronics, IoT, and MCU designs a low-power, cost-effective interconnect option. With CodaCache, MCU teams can also support last-level cache needs and memory performance for AI-driven tasks.
Products for MCU designs
For MCU architects, the right entry point depends on the design bottleneck: interconnect scale, memory locality, coherency, safety, security assurance, or integration throughput.
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