Microcontroller solutions for modern architectures
Enabling the next generation of microcontrollers with innovative network-on-chip (NoC) technology for efficiency, scalability, and safety.
Overview
Scalable solutions for next-gen MCUs
As system-on-chip (SoC) designs grow more complex and data transport needs evolve, traditional buses and crossbars are being replaced by advanced network-on-chip (NoC) interconnect solutions. This transformation addresses the increasing demands for power efficiency, scalability, and integration in modern microcontroller (MCU) architectures.
NoC technology, pioneered by Arteris, leverages packet-based data transfer methods, offering significant advantages in power consumption, performance, and die area utilization, compared to conventional interconnect methods. The comprehensive portfolio of Arteris technologies designed for modern MCUs includes:
- FlexNoC
- FlexWay
- CodaCache
- Magillem
These technologies provide enhanced power efficiency, streamlined interconnect and memory architectures, and simplified design workflows. This is particularly relevant for MCUs powering IoT devices, automotive applications, and industrial systems that demand low power, high reliability, and advanced features like AI and cybersecurity.
Advantages
Built for the demands of modern MCU design
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Optimized PPA
FlexGen, FlexNoC and FlexWay interconnect solutions enhance power, performance, and area efficiency, for advanced MCUs in IoT and industrial applications. Both can be paired with CodaCache which further improves memory access and bandwidth, vital for AI/ML tasks in high-performance MCUs.
Safety
Using Arteris system IP, developers achieve ISO 26262-compliant design, verification, and documentation of safety-critical automotive systems and create ISO 26262-compliant NoCs.
Simplified SoC integration
Magillem tools automate SoC design workflows, supporting IP-XACT standards for faster development cycles and improved collaboration.
Partners
Collaboration around the globe
Arteris collaborates with leading semiconductor vendors and IoT solution providers to deliver optimized interconnect IP solutions for modern MCUs.
Standards
Standards focused for interoperability
From a system design perspective, Arteris supports AMBA protocols, ISO 26262, and other standards for functional safety and interoperability.
Arteris works with partners like Arm by implementing the latest AMBA standards and with Synopsys, Cadence, Alphawave, Blue Cheetah Analog, Innosilicon, and others to align on NoC to controller/PHY interfaces.
FlexWay 5 Core Interconnect IP: A non-coherent, cost-effective interconnect solution
Products
Products for MCU designs
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- EE Journal: Managing the Massive Data Throughput: AI-Based Designs and The Value of NoC Tiling
- EE Journal: The Network-on-Chip Pioneer: How Arteris Enabling SoC Developers to Create Physically Valid NoCs Faster
- Electronic Design: All About NoCs
- SemiWiki: The Impact of Arteris on Automotive and Beyond with Frank Schirrmeister
- SemiWiki: A Broad View of Design Architectures and the Role of the NoC with Arteris’ Michal Siwinski
- EE Journal: The Freedom to Innovate: Arteris and the Rise of RISC-V
- SemiWiki: The Impact of Using a Physically Aware NoC with Charlie Janac
- Arm & Arteris AI and ISO 26262 Presentation
- Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip (SoCs)
- Building Better IP with RTL Architect NoC IP Physical Exploration
- Efficient Scaling of AI Accelerators Using NoC Tiling
- FMEDA Automation for Scalability and Reuse in Complex Systems on Chips (SoCs)
- Is the Missing Safety Ingredient in Automotive AI Traceability?
- Lessons Learned Integrating AI/ML Accelerators into Complex ISO 26262 Compliant Systems-on-Chip
- Safety Considerations for Network-on-Chip (NoC) Development
- The Role of Networks-on-Chips Enabling AI/ML Silicon and Systems
- Tiled Approach to System Scaling
- Magillem Registers – Automate the Hardware/Software Interface for Fast Chip Design
- Accelerating Timing Closure for Networks-on-Chip (NoCs) using Physical Awareness
- Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications
- FlexGen Product Tour
- Integration Challenges for RISC-V Designs
- Promises and Pitfalls of SoC Restructuring
- Scaling Performance in AI Systems
- A Configurable Test Infrastructure using a Mixed-Language and Mixed-Level IP Integration IP-XACT Flow
- A Design Flow for Critical Embedded Systems
- AMS System-Level Verification and Validation using UVM in SystemC and SystemC-AMS: Automotive Use Cases
- Power Dissipation of the Network-on-Chip in a System-on-Chip for MPEG-4 Video Encoding
- Re-Architecting SoCs for the AI Era
- Scalability – A Looming Problem in Safety Analysis
- Security in Artificial Intelligence
- Using Machine Learning for Characterizations of NoC Components
- Using Virtual Prototypes to Improve the Traceability of Critical Embedded Systems Flow
- Boost SoC Efficiency and Speed with FlexGen Smart NoC IP Automation White Paper
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