Our Standards

The Open Compute Project (OCP) advances open hardware designs and specifications for scalable computing infrastructure. Within its Open Domain-Specific Architecture work, OCP’s Bunch of Wires technology supports short-reach die-to-die connectivity for modular silicon systems. Arteris participates in this ecosystem by aligning NoC interfaces with evolving chiplet standards and partner PHYs.

PCI-SIG develops and maintains PCI Express specifications, providing a widely adopted foundation for high-performance connectivity. PCIe also underpins newer chiplet and memory-interconnect ecosystems, including UCIe and CXL. Arteris participates in related standards work and enables NoC-to-controller and PHY alignment for scalable multi-die systems.

Accellera Systems Initiative develops and promotes electronic design and verification standards used across the semiconductor industry, including SystemRDL and technologies that progress into IEEE standards such as IP-XACT and UVM. Arteris implements these standards throughout its SoC integration automation portfolio to improve interoperability, reuse and hardware/software consistency.

CHIPS Alliance is a Linux Foundation project advancing open-source hardware, reusable IP and collaborative silicon-development tools. Its specifications and projects include technologies relevant to interoperable chiplet design, such as the Advanced Interface Bus (AIB). Arteris discusses CHIPS Alliance in its guide to building chiplets while shaping tomorrow’s standards and places open standards at the center of its multi-die solution.

The IEEE Standards Association develops global technical standards that enable interoperability across electronics and semiconductor design. Arteris products rely on IEEE standards including IEEE 1685 IP-XACT for IP packaging, IEEE 1801 UPF for power intent and IEEE 1800.2 UVM for verification. Explore Arteris support for IP-XACT in Magillem, UPF-based power management and UVM verification flows.