AI / Machine Learning Archives

Semiconductor Engineering: Facilitating Complex SoC Design Through Automation And Integration

Automation and integration tools unify IP, connectivity, and software design, enabling scalable, efficient SoC development and reducing manual complexity. Learn more about how unified system definitions, automated interconnect generation, and coordinated design flows improve performance, productivity, and time-to-market in the

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Semiconductor Engineering: Importance Of Hardware Security Verification In Pre-Silicon Design

Security in modern semiconductor design must be built in from the start, not validated after the fact. This article explains how pre-silicon hardware security verification relies on two key pillars — functional verification to ensure security features behave correctly, and

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EDN: Chiplet innovation isn’t waiting for perfect standards

As monolithic SoCs reach their limits, chiplets offer a more scalable and cost-effective path forward. Despite incomplete standards, companies are moving ahead using modular design and flexible interconnects, with Arteris highlighting the role of NoC IP and automation in enabling

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EDN: Last-level cache has become a critical SoC design element

As AI-driven SoCs integrate increasingly heterogeneous compute engines, last-level cache (LLC) has become a critical architectural element for balancing performance, power, and determinism. Positioned between on-chip subsystems and external memory, LLC reduces latency and off-chip traffic but only when carefully

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Semiconductor Engineering: AI Energy Gap and Chiplets: Why Data Movement Matters

At the panel discussion at Chiplet Summit 2026, where Arteris was among the experts, participants emphasized that efficient AI chiplets require more than fast physical links like UCIe—they demand smart, system-level architecture around data movement, coherency, and protocol choice. As

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Electronic Design: Bridging the Gap to Chiplet Interoperability

This article examines the gap between today’s tightly managed multi-die implementations and the long-term vision of true multi-vendor chiplet interoperability. It explains how companies are deploying homogeneous and heterogeneous architectures, why proprietary flows still limit plug-and-play integration, and how standards

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EE Times: The Data Dilemma: Cracking the Code of Data Movement for the Next Wave of Semiconductor Innovation

As semiconductor architectures scale toward chiplets, multi-die SoCs, and AI-driven workloads, data movement—not raw compute—has emerged as the primary limiter of performance, power, and scalability. The article argues that network-on-chip fabrics are becoming the true center of gravity in modern

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Semiconductor Engineering: Solving Real-World AI Bottlenecks

This article explains how modern AI SoCs are increasingly limited by data movement and memory latency rather than raw compute. It highlights the role of efficient interconnects and shared last-level caches in reducing latency, power consumption, and DRAM traffic, and

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EDN: AI workloads demand smarter SoC interconnect design

This EDN article explains how AI workloads are pushing traditional SoC interconnect design beyond practical limits, making intelligent automation essential. Physically aware NoC algorithms optimize topology, power, latency, and timing closure, enabling scalable AI SoCs from data centers to the

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2026 Predictions: System-Level Design, AI-Native Workflows, and the Rise of Multi-Die Compute Fabrics

Explore 2026 semiconductor predictions as AI accelerates system-level design, multi-die compute fabrics, chiplets, 2.5D/3D integration, and AI-native architecture workflows reshape how advanced systems are built and verified.

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