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Semiconductor Engineering: Reducing Avoidable Memory Trips In HBM Systems
As AI and high-performance SoCs increasingly rely on HBM, memory bandwidth alone is no longer enough to maximize performance. This article discusses why the intelligent data movement and cache efficiency are critical to unlocking the full benefits of HBM-based architectures.
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EDN: Last-level cache has become a critical SoC design element
As AI-driven SoCs integrate increasingly heterogeneous compute engines, last-level cache (LLC) has become a critical architectural element for balancing performance, power, and determinism. Positioned between on-chip subsystems and external memory, LLC reduces latency and off-chip traffic but only when carefully
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Semiconductor Engineering: Reducing SoC Power With NoCs And Caches
The growing complexity of integrating multiple processing elements, memory systems and communication interfaces into a single SoC demands innovative solutions to optimize power efficiency. Arteris offers a comprehensive suite of IP products, including FlexNoC, Ncore and CodaCache that address these
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