FlexGen Archives

Semiconductor Engineering: Facilitating Complex SoC Design Through Automation And Integration

Automation and integration tools unify IP, connectivity, and software design, enabling scalable, efficient SoC development and reducing manual complexity. Learn more about how unified system definitions, automated interconnect generation, and coordinated design flows improve performance, productivity, and time-to-market in the

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Design & Reuse: Topology and Data Movement in Multi-Die Design

This article explores how multi-die design shifts the primary challenge from scaling silicon to managing data movement and system integration across chiplets. It highlights the critical role of NoC topology in controlling traffic, latency, and coherency between dies, as well

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EDN: Last-level cache has become a critical SoC design element

As AI-driven SoCs integrate increasingly heterogeneous compute engines, last-level cache (LLC) has become a critical architectural element for balancing performance, power, and determinism. Positioned between on-chip subsystems and external memory, LLC reduces latency and off-chip traffic but only when carefully

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Semiconductor Engineering: Solving Real-World AI Bottlenecks

This article explains how modern AI SoCs are increasingly limited by data movement and memory latency rather than raw compute. It highlights the role of efficient interconnects and shared last-level caches in reducing latency, power consumption, and DRAM traffic, and

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EDN: AI workloads demand smarter SoC interconnect design

This EDN article explains how AI workloads are pushing traditional SoC interconnect design beyond practical limits, making intelligent automation essential. Physically aware NoC algorithms optimize topology, power, latency, and timing closure, enabling scalable AI SoCs from data centers to the

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2026 Predictions: System-Level Design, AI-Native Workflows, and the Rise of Multi-Die Compute Fabrics

Explore 2026 semiconductor predictions as AI accelerates system-level design, multi-die compute fabrics, chiplets, 2.5D/3D integration, and AI-native architecture workflows reshape how advanced systems are built and verified.

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Semiconductor Engineering: Efficiency Defines The Future Of Data Movement

As AI workloads expand and chiplet architectures evolve, data movement now consumes more energy than computation itself. Achieving higher performance within fixed power budgets demands efficient, intelligent interconnects and automation across multi-die SoC designs. Learn more in the article.

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Semiconductor Engineering: The Future Of SoC Design Is Data Movement

The semiconductor industry is shifting from focusing on raw compute to tackling the growing challenge of data movement in complex SoCs. With advances in chiplets, high-bandwidth memory, CXL fabrics, and automotive zonal architectures, predictable performance now depends on layered, automated,

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Semiconductor Engineering: A Smarter Path To Chiplets Through An Enhanced Multi-Die Solution

With monolithic SoCs reaching their limits, chiplet-based architectures are key to building flexible, high-performance systems. Arteris’ multi-die solution combines silicon-proven NoC IP, cache coherency, and automation tools to streamline chiplet integration and accelerate time-to-market. Learn more in the article.

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RISC-V: Arteris’ Multi-Die Solution for the RISC-V Ecosystem

As AI, HPC, and automotive workloads push past the limits of monolithic SoCs, chiplet-based design offers a scalable and cost-efficient path forward. Arteris enables this shift with advanced NoC IP for coherent and non-coherent multi-die interconnects, UCIe-based die-to-die links, and

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