FlexNoC Archives

Semiconductor Engineering: Using SystemC TLM Modeling To Solve AI Data Movement Challenges

SystemC TLM modeling helps AI chip architects analyze NoC data movement early, identify bandwidth and latency bottlenecks, optimize workload behavior, and reduce RTL-stage performance and integration risk. Learn more about how early NoC modeling improves AI system design and accelerates

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EDN: How data movement defines performance for AI silicon

This article explores how AI chip performance is increasingly constrained by data movement rather than raw compute power, highlighting the growing role of network-on-chip (NoC) architectures, chiplets, cache hierarchies, and physically aware design in modern AI SoCs. Learn more about

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Design & Reuse: Topology and Data Movement in Multi-Die Design

This article explores how multi-die design shifts the primary challenge from scaling silicon to managing data movement and system integration across chiplets. It highlights the critical role of NoC topology in controlling traffic, latency, and coherency between dies, as well

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Semiconductor Engineering: Importance Of Hardware Security Verification In Pre-Silicon Design

Security in modern semiconductor design must be built in from the start, not validated after the fact. This article explains how pre-silicon hardware security verification relies on two key pillars — functional verification to ensure security features behave correctly, and

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Critical Safety Overview and Definitions

Overview of critical safety systems and functional safety standards in automotive, focusing on ISO 26262 compliance and its impact on SoC design and performance.

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NoC Interconnect IP Improves SoC Power, Performance and Area

Explore how Arteris' NoC interconnect IP enhances SoC power efficiency, performance, and area, driving advancements in complex semiconductor designs.

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SoC Interconnect Fabric: A Brief History from Buses to the NoCs of Today and Tomorrow

Explore the evolution of SoC interconnect fabrics from buses to advanced NoCs, highlighting their impact on modern high-performance computing and efficient system integration.

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Semiconductor Engineering: A Smarter Path To Chiplets Through An Enhanced Multi-Die Solution

With monolithic SoCs reaching their limits, chiplet-based architectures are key to building flexible, high-performance systems. Arteris’ multi-die solution combines silicon-proven NoC IP, cache coherency, and automation tools to streamline chiplet integration and accelerate time-to-market. Learn more in the article.

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RISC-V: Arteris’ Multi-Die Solution for the RISC-V Ecosystem

As AI, HPC, and automotive workloads push past the limits of monolithic SoCs, chiplet-based design offers a scalable and cost-efficient path forward. Arteris enables this shift with advanced NoC IP for coherent and non-coherent multi-die interconnects, UCIe-based die-to-die links, and

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EDN: Chiplet design basics for engineers

As AI and HPC workloads intensify, engineers are turning to chiplet-based architectures to overcome the limitations of traditional SoCs. This article explains the fundamentals of chiplet design, its advantages, and the tools enabling scalable, high-performance multi-die systems.

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