FlexNoC

Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards

FlexNoC 5 interconnect IP with physical awareness improves place and route efficiency and reduces interconnect area and power consumption.

November 19, 2024 Continue Reading
Arteris and MIPS Partner on High-Performance RISC-V SoCs for Automotive, Datacenter and Edge Al
Arteris and MIPS Partner on High-Performance RISC-V SoCs for Automotive, Datacenter and Edge AI

Pre-verified reference platform supports the acceleration of RISC-V-based SoC designs with mutual customers.

November 12, 2024 Continue Reading
Tenstorrent Deploys Arteris IP in Next-Gen Chiplet Announcement
Tenstorrent Expands Deployment of Arteris’ Network-on-Chip IP to Next-Generation of Chiplet-Based AI Solutions

Arteris’ FlexNoC interconnect IP optimizes the on-chip communication flow supporting superior performance, power and area for advancing AI chip and chiplet computing.

November 5, 2024 Continue Reading
Today’s SoCs typically feature multiple clock and power domains
Semiconductor Engineering: Reducing SoC Power With NoCs And Caches

The growing complexity of integrating multiple processing elements, memory systems and communication interfaces into a single SoC demands innovative solutions to optimize power efficiency. Arteris offers a comprehensive suite of IP products, including FlexNoC, Ncore and CodaCache that address these challenges.

October 31, 2024 Continue Reading
Arteris Selected by TIER IV for Intelligent Vehicles
Arteris Selected by TIER IV for Intelligent Vehicles

TIER IV has licensed Arteris’ FlexNoC 5 interconnect IP and Magillem Connectivity SoC integration automation software for its next generation of intelligent vehicle electronics.

October 29, 2024 Continue Reading
Simplified representation of a soft-IP and NoC-based SoC
Design & Reuse: Accelerating SoC Evolution With NoC Innovations Using NoC Tiling for AI and Machine Learning

A new trend is emerging in the design of high-end, multi-billion-transistor system-on-chip (SoC) devices and it is called “NoC tiling”. It’s an innovative approach that facilitates scaling, condenses design time, speeds testing, and reduces risk.

October 28, 2024 Continue Reading

Recent Articles

SemiWiki: How Arteris FlexGen Smart NoC IP Democratizes Advanced Chip Design

How Can Network On-Chip IP Can Meet System-On-Chip Demands?

Verification Experts Vs. Generalists

EDN: How AI is changing the game for high-performance SoC designs

RISC-V: Soft Tiling RISC-V Processor Clusters Speed Design and Reduce Risk

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