Magillem Connectivity Archives

Semiconductor Engineering: A Golden Source As The Single Source Of Truth In HSI

Maintaining alignment between hardware and software is one of the biggest challenges in complex SoC design. A single, machine-readable golden source keeps every element from RTL to drivers and documentation perfectly synchronized. Learn how Arteris’ Magillem Platform makes this possible

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EE Times: A Guide to Building Chiplets Today While Shaping Tomorrow’s Standards

Chiplet standards like UCIe, AIB, and BoW are still evolving, but design teams can start building with chiplets today by adopting packaging automation, structured IP metadata, and scalable interconnect fabrics that enable flexibility and future-proof integration. Learn how to design

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Design & Reuse: Efficient IP Packaging for Today’s SoC Integration

As SoC architectures scale in complexity, managing hundreds of IP blocks consistently from concept through production is critical to avoid costly errors and rework. Standardizing IP descriptions with IEEE 1685 (IP-XACT) and automating packaging ensures interoperability, accelerates design, and promotes

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Semiconductor Engineering: System Integration With Standards-Based Automation

As SoCs evolve into complex multi-die systems, standards-based automation is key. Learn how IP-XACT and Arteris’ Magillem tools enable consistent metadata, scalable IP reuse, and faster, error-free integration across teams and tools.

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EDN: Chiplet design basics for engineers

As AI and HPC workloads intensify, engineers are turning to chiplet-based architectures to overcome the limitations of traditional SoCs. This article explains the fundamentals of chiplet design, its advantages, and the tools enabling scalable, high-performance multi-die systems.

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