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Design & Reuse: Efficient IP Packaging for Today’s SoC Integration
As SoC architectures scale in complexity, managing hundreds of IP blocks consistently from concept through production is critical to avoid costly errors and rework. Standardizing IP descriptions with IEEE 1685 (IP-XACT) and automating packaging ensures interoperability, accelerates design, and promotes
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Semiconductor Engineering: System Integration With Standards-Based Automation
As SoCs evolve into complex multi-die systems, standards-based automation is key. Learn how IP-XACT and Arteris’ Magillem tools enable consistent metadata, scalable IP reuse, and faster, error-free integration across teams and tools.
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EDN: Chiplet design basics for engineers
As AI and HPC workloads intensify, engineers are turning to chiplet-based architectures to overcome the limitations of traditional SoCs. This article explains the fundamentals of chiplet design, its advantages, and the tools enabling scalable, high-performance multi-die systems.
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Semiconductor Engineering: CSR Management: Life Beyond Spreadsheets
The hardware-software interface (HSI) that’s physically represented by control and status registers (CSRs) is a critical source of design risk. Mismanagement of CSRs contributes to a number of SoC failures. To avoid these setbacks, engineering teams need a robust, automated
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Design & Reuse: Automating Hardware-Software Consistency in Complex SoCs
Magillem Registers automates hardware-software consistency, ensuring consistency, reducing errors, and accelerating development for efficient, innovative, and reliable designs.
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