Multi-Die Archives

EE Times: The Data Dilemma: Cracking the Code of Data Movement for the Next Wave of Semiconductor Innovation

As semiconductor architectures scale toward chiplets, multi-die SoCs, and AI-driven workloads, data movement—not raw compute—has emerged as the primary limiter of performance, power, and scalability. The article argues that network-on-chip fabrics are becoming the true center of gravity in modern

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2026 Predictions: System-Level Design, AI-Native Workflows, and the Rise of Multi-Die Compute Fabrics

Explore 2026 semiconductor predictions as AI accelerates system-level design, multi-die compute fabrics, chiplets, 2.5D/3D integration, and AI-native architecture workflows reshape how advanced systems are built and verified.

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Advancing Europe’s Automotive Chiplet Vision: Arteris Joins CHASSIS to Accelerate Software-Defined Mobility

Arteris joins CHASSIS, Europe’s open automotive chiplet initiative with advanced NoC and multi-die interconnect technology that accelerates software-defined mobility.

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Semiconductor Engineering: Efficiency Defines The Future Of Data Movement

As AI workloads expand and chiplet architectures evolve, data movement now consumes more energy than computation itself. Achieving higher performance within fixed power budgets demands efficient, intelligent interconnects and automation across multi-die SoC designs. Learn more in the article.

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EE Times: A Guide to Building Chiplets Today While Shaping Tomorrow’s Standards

Chiplet standards like UCIe, AIB, and BoW are still evolving, but design teams can start building with chiplets today by adopting packaging automation, structured IP metadata, and scalable interconnect fabrics that enable flexibility and future-proof integration. Learn how to design

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Semiconductor Engineering: The Future Of SoC Design Is Data Movement

The semiconductor industry is shifting from focusing on raw compute to tackling the growing challenge of data movement in complex SoCs. With advances in chiplets, high-bandwidth memory, CXL fabrics, and automotive zonal architectures, predictable performance now depends on layered, automated,

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Electronic Design: Speeding the Process of Building IPs, Chiplets, and SoCs

Designing modern SoCs and multi-die systems requires faster integration of thousands of IP blocks and chiplets while minimizing errors. Structured metadata standards like IP-XACT, combined with automation, are transforming this process by ensuring consistency, tool interoperability, and accurate hardware/software alignment

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Semiconductor Engineering: A Smarter Path To Chiplets Through An Enhanced Multi-Die Solution

With monolithic SoCs reaching their limits, chiplet-based architectures are key to building flexible, high-performance systems. Arteris’ multi-die solution combines silicon-proven NoC IP, cache coherency, and automation tools to streamline chiplet integration and accelerate time-to-market. Learn more in the article.

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RISC-V: Arteris’ Multi-Die Solution for the RISC-V Ecosystem

As AI, HPC, and automotive workloads push past the limits of monolithic SoCs, chiplet-based design offers a scalable and cost-efficient path forward. Arteris enables this shift with advanced NoC IP for coherent and non-coherent multi-die interconnects, UCIe-based die-to-die links, and

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EDN: Chiplet design basics for engineers

As AI and HPC workloads intensify, engineers are turning to chiplet-based architectures to overcome the limitations of traditional SoCs. This article explains the fundamentals of chiplet design, its advantages, and the tools enabling scalable, high-performance multi-die systems.

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