Network-on-Chip (NoC) Archives

HPCwire: Data Center AI at the Power Limit: When Data Movement Defines Performance

This article explains how power limits are reshaping data center AI design, making efficient, predictable data movement across heterogeneous compute, memory and chiplet architectures central to system performance. He highlights the role of intelligent interconnect and automation in keeping compute

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Semiconductor Engineering: A Network-on-Chip (NoC) For Multi-Die Devices

This article explains how extending native NoC packet traffic across die boundaries can support efficient, scalable data movement for multi-die systems, especially physical AI and automotive platforms.

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SoC and NoC in the Chiplet Era: Understanding Modern SoC Architecture

Learn how SoCs and NoCs work together in modern semiconductor design and why chiplet-based architectures make intelligent data movement more critical than ever.

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Semiconductor Engineering: How Cache Coherency Simplifies AI Software

This article explains how hardware-managed cache coherency can simplify AI software by coordinating shared data across CPUs, accelerators and chiplets. The article highlights the role of coherent and non-coherent interconnects in building scalable, efficient AI SoCs, while presenting Arteris’ Ncore,

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TechRadar: Data movement is the new performance battleground in semiconductor design

The article highlights why interconnect design must become a first-class architectural consideration, with quality of service, determinism and physically aware automation playing key roles across AI data centers, physical AI and multi-die systems.

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Electronic Design: The Missing Layer in AI Systems Design is Predictable, Scalable Data Movement

The article explores why predictable, scalable data movement is becoming a critical architectural requirement for AI systems as compute complexity and bandwidth demands continue to grow.

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Embedded: Last-Level Caches Matter Even More in the HBM Era

The article explains why last-level caches (LLCs) are becoming even more important as high-bandwidth memory (HBM) is adopted for AI and high-performance computing.

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Advancing Europe’s Automotive Innovation Ecosystem: Arteris Continues Its Work in the RIGOLETTO Project

As software-defined vehicles reshape the automotive industry, collaborative innovation is becoming essential to developing secure, scalable computing platforms. Learn how Arteris is contributing to the European RIGOLETTO project, helping advance next-generation automotive architectures through expertise in Network-on-Chip technology, RISC-V integration,

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The AI Journal: Making chiplets work for AI requires more than connectivity

This article explains why building successful AI chiplet architectures requires more than high-speed die-to-die connectivity. It explores how efficient data movement, protocol selection, coherency, and intelligent NoC architecture are critical to maximizing performance, scalability, and energy efficiency in next-generation AI

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EDN: Model your IPs and your NoCs

As SoC and chiplet architectures become increasingly complex, effective modeling must extend beyond functional IP blocks to include the NoC interconnect fabric itself. This article highlights why NoCs have become critical determinants of system performance and explains the value of

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