IP-XACT Register Training
Our 2-day training will accelerate your ability to automate memory map and register definition, generation and configuration which will greatly aid your product documentation and software / firmware development efforts. Let us help you become a register management ninja!
IP-XACT Register Training Syllabus
Day 1:
9 am - 1 pm: IP-XACT elements for registers
- Memory Maps
- Registers blocks and dimensional
- Registers and dimensional
- Bitfields
- Enumerations
- Alternate registers
2 pm - 6 pm: Special registers representation
- Templated registers
- Templated bitfields
- Wide bitfields
- Other registers (indirect, shadow…)
Day 2:
9 am - 1 pm: Register configurability and system
- Configurable register elements
- Model parameters
- Choices
- Setting and resolving register configurable elements
- Slave Bus Interface and Memory Map
- Design and system map
- Tight Generator Interface (TGI)
- Generator chains