AMBA AXI, AHB, OCP and other with Arteris Network-on-Chip interconnects

Network-on-Chip Interconnect IP Addresses System-on-Chip Designers' Needs …

Arteris interconnect IP has been chosen by 6 of the top 10 semiconductor makers targeting many applications including automotive, video, networking, and mobile-phone processors. Its highly scalable architecture provides an elegant solution for designs ranging from the simple, with just a handful of IPs, to complex, with well over 100 IPs.

Interconnect IP

Arteris' patented Network-on-Chip (NoC) interconnect IP technology provides a flexible and scalable solution that allows each designer to optimize and achieve the specific design goals for their particular design. Take advantage of fewer wires, less routing congestion, faster timing closure, less die area, less schedule risk, and easier derivative creation with these Arteris network-on-chip IP products:

Springer Verlag Journal Design Automation for Embedded Systems peer reviewed article by Arteris

Automated Configuration and Verification

Arteris IP products include tooling that automates the creation of the interconnect based on the SoC requirements. Arteris’ tool suite configures all the design elements required to build an interconnect, such as switches, protocol converters, synchronizers, width converters, and power domain isolators. These elements are connected through links that carry information in packets — basically encapsulated burst transactions. Because packetized signals are decoupled from physical links, interconnect design is simple and flexible. And with the Arteris IP configuration tool suite and automated verification environment, design and verification can be done easily, in a matter of days or even hours.

With reusable IP blocks, SoC integration has become the critical development phase that determines design quality and the tape out schedule. The interconnect design is the key component of SoC integration. Arteris provides designers the ability to easily generate, optimize and automatically verify the interconnect IP at each stage of the project as well as certainty in timing convergence, which brings reliability and predictability in the design and tape out schedule.

wire routing congestion presentation routing congestion solved by network on chip interconnect for SoC