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Arteris provides network-on-chip (NoC) interconnect IP and System Integration Automation tools to improve performance, power consumption and die size of system-on-chip (SoC) devices for consumer electronics, mobile, automotive and other applications. Over 3 billion devices have been shipped to date containing Arteris IP.

Coherent Interconnect

Ncore IP tackles multicore SoC challenges through heterogeneous coherency, efficient caching, and high throughput for reliable, high-performance SoCs.

Non-Coherent Interconnect

Essential for efficient NoC designs, our high-end Flex family of products bring physical awareness to accelerate timing closure, reduce wires and increase SoC performance.

Category Features FlexWay FlexNoC FlexGen
Target Audience and Scale Smaller-scale MCU SoCs
Small-medium scale SoCs
Large scale SoCs
Instances Per Design Single NoC instance
Multiple NoC instances
Network Interface Units (NIUs) Up to 50 NIUs
Up to 200 NIUs
Up to 1000 NIUs with XL option with XL option
Compatibility AXI, AHB, APB, OCP, PIF, AMBA5
ACE-Lite
Smart NoC Automation Topology generation with minimum wire length
Scripting-driven regular topology creation
Incremental design capability
Physical Awareness Automatic timing closure assistance
Floorplan visualization
Advanced Scalability NIU tiling with XL option with XL option
Mesh topology editor with XL option with XL option
Write broadcast stations with XL option with XL option
Virtual channel links with XL option with XL option
Source synchronous asynchronous bridges with XL option with XL option
Up to 1024 bits data bus with XL option with XL option
512 pending transaction support with XL option with XL option
Optimizations Optimization for performance, area and wire length
Advanced Quality of Service (QoS)
Power management and security
Address and data protection schemes
Advanced in-circuit debug features
Multi-cycle SRAM support
Floorplan visualization
Add-on Options Memory Re-order Buffer option
Reliability option
Safety (up to ISO 26262 ASIL D) option
Advanced Scalability (XL) option
Markets Automotive, Communications, Consumer Electronics, Enterprise Computing and Industrial Markets

Last-Level Cache

CodaCache IP optimizes SoC performance by minimizing memory latency. This highly configurable shared cache improves data flow and power efficiency.

SoC Connectivity

SoC Assembly with efficient handling of all aspects of system integration to make the design process easier, faster, and less risky, making the most of design teams’ productivity and expertise.

Hardware / Software Interface

A single source of truth environment enabling effective collaborative development of the software and hardware interface, keeping all design teams in sync while mitigating design errors.

Traceability

Traceability refers to the ability to follow the life of a unit of design and its dependencies from requirement to implementation in both forward and backward directions.