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Arteris provides network-on-chip (NoC) interconnect IP and System Integration Automation tools (SIA) to improve performance, power consumption and die size of system-on-chip (SoC) devices for consumer electronics, mobile, automotive and other applications. Over 3 billion devices have been shipped to date containing Arteris IP.

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Non-Coherent Interconnect
Non-Coherent Interconnect IP
FlexNoC 5 Interconnect IP

Physically aware NoC with ISO26262 support option delivering up to 5X shorter turn-around-time on timing closure versus manual physical iterations.

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FlexWay icon
Non-Coherent Interconnect IP
FlexWay Interconnect IP

Particularly well suited to cost-efficient, low-power Internet-of-Things (IoT) edge devices, also available with ISO26262 support.

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Coherent Interconnect

Coherent Interconnect
Ncore Cache Coherent Interconnect IP

Efficient coherent NoC interconnect that addresses key challenges in multi-core ASIC designs ensuring reliability, ISO26262 support, and optimized performance.

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Last-Level Cache

Last-Level Cache
CodaCache Last-Level Cache IP

A last-level cache IP that solves key SoC challenges like performance, data access, timing closure, and layout congestion with a configurable caching solution.

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SoC Connectivity
SoC Connectivity
Magillem Connectivity

Shorten, streamline, and de-risk the integration process through automation and built-in checkers to boost productivity, accelerating TTM and improving design quality.

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Hardware / Software Interface
Hardware / Software Interface
Hardware / Software Interface
Magillem Register

Import memory map description in a single source of truth environment, ensuring synchronization between HW, SW, and documentation for automatic, consistent data generation.

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Hardware / Software Interface
CSRCompiler

True cross-compiler engine producing all required views, to the entire team, for the development of the hardware/software interface with highest quality and performance.

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Traceability
Traceability
Harmony Trace

Harmony Trace offers Seamless Traceability and Quality Management in SoC design flows, providing enhanced design data intelligence.

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