FlexNoC Interconnect IP
Physically Aware Network-on-Chip IP
Enabling SoC Developers to Create Physically Valid NoCs Faster
The world’s #1 on-chip fabric is used by the world’s top semiconductor design teams as the backbone on-chip communications for chips targeting the fastest growing markets.
The latest generation FlexNoC Interconnect with its integrated physical awareness technology, gives place and route teams a much better starting point while simultaneously reducing interconnect area and power consumption. FlexNoC delivers up to 5X shorter turn-around-time versus manual physical iterations.
The combined use of FlexNoC and Ncore IP in an ASIC design delivers unparalleled performance optimization, scalability, and system integration, enabling robust cache coherence, efficient communication, and flexibility, leading to market differentiation and accelerated time-to-market.
The Most Complete Network-On-Chip Product
Everything design teams need to create the world’s best SoCs, faster
Flexible Topologies
FlexNoC is generated from simple elementary components which are combined by a powerful set of underlying algorithms and an intuitive GUI, making it possible to build any topology.
Small to Large SoCs
FlexNoC easily supports long cross-chip paths by leveraging source-synchronous communications and virtual channels.
Huge Bandwidth
FlexNoC drives performant on-chip data flow and access to off-chip memory by enabling multi-channel HBMx memory and high bandwidth data paths.
FlexNoC Key Features
- Auto-timing closure assist
- NIU (Network Interface Unit) tiling to organize NIUs into modular, repeatable blocks, improving scalability, efficiency, and reliability
- Topology visualized directly on floorplan
- Multi-clock/power/voltage domains and power management with unit-level clock gating
- Multi-protocol support including AMBA 5 with QoS bandwidth regulator and limiter Enumerations
- General optimizations for lower area e.g. up to 30% for some NoC elements depending on configuration
- Native and user-defined firewall security
- Import and export to Magillem tools
- AMBA 5 support of DVM 8.1 (Distributed Virtual Memory)
- On-chip performance monitoring and debug
- Debug and trace with ATB 128b and timestamps
Explore additional features of FlexNoC, download the datasheet.
Feature Spotlight
NoC tiling - new feature with FlexNoC
NoC tiling with mesh topology for NPUs, GPUs, TPUs with FlexNoC. Up to 1024 tiles.
- Scale performance
- Condense design time
- Speed testing
- Reduce design risk
Create modular, scalable designs, enabling faster integration, verification and optimization.
Efficient Transport of Data Through the SoC
Arteris CodaCache® last-level cache
- Ideal for NoC applications with data re-use
- Improves overall SoC latency and power
Learn about CodaCache
NoC Integration Automated Flow
Automated flow to leverage SoC connectivity information:
- Improved productivity with reduced process
- Better quality with early errors detections thanks to the checkers
Learn about Magillem Connectivity and Magillem Registers
FlexNoC Product Benefits
Higher Frequencies, Lower Latencies
Using built-in NoC performance analysis exploration tools
Lower Power Consumption
Advanced power management through clock gating, DVFS and GALS
Smaller Die Area
Fewer wires using optimal NoC transport layer
Speedy Timing Closure
Early physical awareness for faster convergence without re-designs
Easy Configuration
Through the intuitive FlexNoC UI
Automated Verification
Saving hundreds of hours of work versus manual verification test benches
Shorter Schedules
Fewer iteration loops
Higher Profit
Reduced TTM from FlexNoC design efficiency savings
Read more about why we are unique on our NoC Technology page.
FlexNoC Product Options
Seamlessly integrated extensions to the base FlexNoC feature set
Product Comparison Table
| Category | Features | FlexWay | FlexNoC | FlexGen |
|---|---|---|---|---|
| Target Audience and Scale | Smaller-scale MCU SoCs | ✓ | ✓ | ✓ |
| Small-medium scale SoCs | ✓ | ✓ | ||
| Large scale SoCs | ✓ | ✓ | ||
| Instances Per Design | Single NoC instance | ✓ | ✓ | ✓ |
| Multiple NoC instances | ✓ | ✓ | ||
| Network Interface Units (NIUs) | Up to 50 NIUs | ✓ | ✓ | ✓ |
| Up to 200 NIUs | ✓ | ✓ | ||
| Up to 1000 NIUs | with XL option | with XL option | ||
| Compatibility | AXI, AHB, APB, OCP, PIF, AMBA5 | ✓ | ✓ | ✓ |
| ACE-Lite | ✓ | ✓ | ||
| Smart NoC Automation | Topology generation with minimum wire length | ✓ | ||
| Scripting-driven regular topology creation | ✓ | |||
| Incremental design capability | ✓ | |||
| Physical Awareness | Automatic timing closure assistance | ✓ | ✓ | |
| Floorplan visualization | ✓ | ✓ | ||
| Advanced Scalability | NIU tiling | with XL option | with XL option | |
| Mesh topology editor | with XL option | with XL option | ||
| Write broadcast stations | with XL option | with XL option | ||
| Virtual channel links | with XL option | with XL option | ||
| Source synchronous asynchronous bridges | with XL option | with XL option | ||
| Up to 1024 bits data bus | with XL option | with XL option | ||
| 512 pending transaction support | with XL option | with XL option | ||
| Optimizations | Optimization for performance, area and wire length | ✓ | ||
| Advanced Quality of Service (QoS) | ✓ | ✓ | ✓ | |
| Power management and security | ✓ | ✓ | ✓ | |
| Address and data protection schemes | ✓ | ✓ | ✓ | |
| Advanced in-circuit debug features | ✓ | ✓ | ✓ | |
| Multi-cycle SRAM support | ✓ | ✓ | ✓ | |
| Floorplan visualization | ✓ | ✓ | ||
| Add-on Options | Memory Re-order Buffer option | ✓ | ✓ | ✓ |
| Reliability option | ✓ | ✓ | ✓ | |
| Safety (up to ISO 26262 ASIL D) option | ✓ | ✓ | ✓ | |
| Advanced Scalability (XL) option | ✓ | ✓ | ||
| Markets | Automotive, Communications, Consumer Electronics, Enterprise Computing and Industrial Markets | ✓ | ✓ | ✓ |
Sondrel has deployed Arteris FlexNoC interconnect IP across several customer SoC projects to great effect. Physical constraints have always been an important issue and are even more important below 16nm geometries. The latest FlexNoC 5 with its physical awareness technology, enables our RTL teams to verify that architectures meet physical constraints and provide a better starting point for our place and route team. We look forward to our continued cooperation with Arteris.
Sondrel
Graham Curren, CEO of Sondrel
Using Arteris FlexNoC allows us to reduce development time and manage project risk. FlexNoC’s advanced quality-of-service and debugging features, combined with its multi-protocol support, allow Samsung SUHD TVs to reduce power consumption and die area for complex chips with more than 100 IP interfaces.
Samsung
HaeJoo Jeong, Vice President, Visual Display Business, Samsung Electronics
FlexNoC interconnect IP allowed us to dramatically increase MCU performance and functionality with no impact on die area while significantly decreasing power consumption.
Renesas
Andreas Papliolios, Director of IoT Silicon, Renesas Electronics America
As a result of our thorough evaluation, we know the Arteris FlexNoC interconnect IP will help us shorten development schedules and increase product performance, while simultaneously decreasing costs due to back-end wire routing congestion and timing closure issues.
Toshiba
Yukihiro Urakawa, Senior Manager, Logic LSI Division of Semiconductor & Storage Products Company, Toshiba Corporation
By incorporating Arteris FlexNoC interconnect IP into our development programs, we are able to streamline our overall design time. This solution also provides us with flexibility to create derivations of our offerings to quickly adapt to changing market needs.
Rambus
Mike Uhler, Vice President, Emerging Solutions Division, Rambus
TSMC chose to work with Arteris on the interposer based test chip program because its interconnect technology is ideally suited to addressing the SoC wire routing congestion and timing closure challenges. TSMC and Arteris are working together to make it easier for our joint customers to adopt these technologies.
TSMC
Suk Lee, Director of Design Infrastructure Marketing, TSMC
Our successful adoption of Arteris FlexNoC fabric IP has been straightforward, allowing us to more quickly architect and implement sophisticated systems-on-chip in less time and with better power consumption and performance.
Freescale
Fares Bagh, Vice President of R&D, Freescale
- FlexNoC Datasheet
- Infographic: Accelerating Timing Closure for Networks-on-Chip (NoCs) With Physical Awareness
- Video: Scaling Performance In AI Systems | Semiconductor Engineering
- Webinar: Arteris FlexNoC 5 – Industry’s First Physically Aware Network-on-Chip IP
- Blogs
- Managing the Massive Data Throughput: AI-Based Designs and The Value of NoC Tiling | EE Journal
- Reducing SoC Power With NoCs And Caches | Semiconductor Engineering
- All About NoCs | Electronic Design
- Accelerating SoC Evolution With NoC Innovations Using NoC Tiling for AI and Machine Learning | Design & Reuse
- Why NoC tiling matters in AI-centric SoC designs | EDN
- Physically Aware Network-on-Chip Streamlines SoC Design Cycle | Electronic Design
- How Physically Aware Interconnect IP Bolsters SoC Design | EDN
- Considering Semiconductor Implementation Aspects Early During Network-On-Chip Development | Semiconductor Engineering
- Podcast: The Impact of Using a Physically Aware NoC with Charlie Janac | SemiWiki
- Meet the Next-Generation Network-on-Chip From Arteris | Design & Reuse
- Physically Aware NoCs | Semiconductor Engineering
- The Network-on-Chip Pioneer: How Arteris Enabling SoC Developers to Create Physically Valid NoCs Faster | EE Journal
- Press Releases
- Arteris Selected by Nextchip to Accelerate Chip Designs for Automotive Vision Technology | Mar 18, 2025
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards | Nov 19, 2024
- Arteris and MIPS Partner on High-Performance RISC-V SoCs for Automotive, Datacenter and Edge AI | Nov 12, 2024
- Arteris Selected by TIER IV for Intelligent Vehicles | Oct 29, 2024