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FlexNoC Interconnect IP

Physically Aware Network-on-Chip IP

Overview

Enabling SoC Developers to Create Physically Valid NoCs Faster

The world’s #1 on-chip fabric is used by the world’s top semiconductor design teams as the backbone on-chip communications for chips targeting the fastest growing markets.

The latest generation FlexNoC Interconnect with its integrated physical awareness technology, gives place and route teams a much better starting point while simultaneously reducing interconnect area and power consumption. FlexNoC delivers up to 5X shorter turn-around-time versus manual physical iterations.

The combined use of FlexNoC and Ncore IP in an ASIC design delivers unparalleled performance optimization, scalability, and system integration, enabling robust cache coherence, efficient communication, and flexibility, leading to market differentiation and accelerated time-to-market.

Advantages

The Most Complete Network-On-Chip Product

Everything design teams need to create the world’s best SoCs, faster

Flexible Topologies

FlexNoC is generated from simple elementary components which are combined by a powerful set of underlying algorithms and an intuitive GUI, making it possible to build any topology.

Small to Large SoCs

FlexNoC easily supports long cross-chip paths by leveraging source-synchronous communications and virtual channels.

Huge Bandwidth

FlexNoC drives performant on-chip data flow and access to off-chip memory by enabling multi-channel HBMx memory and high bandwidth data paths.

FlexNoC 5 Key Features

Auto-timing closure assist
NIU (Network Interface Unit) tiling to organize NIUs into modular, repeatable blocks, improving scalability, efficiency, and reliability
Topology visualized directly on floorplan
Multi-clock/power/voltage domains and power management with unit-level clock gating
Multi-protocol support including AMBA 5 with QoS bandwidth regulator and limiter Enumerations
General optimizations for lower area e.g. up to 30% for some NoC elements depending on configuration
Native and user-defined firewall security
Import and export to Magillem tools
AMBA 5 support of DVM 8.1 (Distributed Virtual Memory)
On-chip performance monitoring and debug
Debug and trace with ATB 128b and timestamps

Explore additional features of FlexNoC, download the datasheet.

Feature Spotlight

NoC tiling — new feature with FlexNoC

NoC tiling with mesh topology for NPUs, GPUs, TPUs with FlexNoC. Up to 1024 tiles.

Scale performance
Condense design time
Speed testing
Reduce design risk

Create modular, scalable designs, enabling faster integration, verification and optimization.

Efficient Transport of Data Through the SoC

Arteris CodaCache® last-level cache:

Ideal for NoC applications with data re-use
Improves overall SoC latency and power

Efficient Transport of Data Through the SoC

NoC Integration Automated Flow

Automated flow to leverage SoC connectivity information:

Improved productivity with reduced process
Better quality with early errors detections thanks to the checkers

NoC Integration Automated Flow

FlexNoC Product Benefits

Higher Frequencies,  Lower Latencies

Using built-in NoC performance analysis exploration tools

Lower Power Consumption

Advanced power management through clock gating, DVFS and GALS

Smaller Die Area

Fewer wires using optimal NoC transport layer

Speedy Timing Closure

Early physical awareness for faster convergence without re-designs

Easy Configuration

Through the intuitive FlexNoC UI

Automated Verification

Saving hundreds of hours of work versus manual verification test benches

Shorter Schedules

Fewer iteration loops

Higher Profit

Reduced TTM from FlexNoC design efficiency savings

Product Comparison Table

Category	Features	FlexNoC	FlexGen
Target Audience and Scale	Smaller-scale MCU SoCs
	Small-medium scale SoCs
	Large scale SoCs
Instances Per Design	Single NoC instance
Instances Per Design	Multiple NoC instances
Network Interface Units (NIUs)	Up to 50 NIUs
	Up to 200 NIUs
	Up to 1000 NIUs	with XL option	with XL option
Compatibility	AXI, AHB, APB, OCP, PIF, AMBA5
Compatibility	ACE-Lite
Smart NoC Automation	Topology generation with minimum wire length
	Scripting-driven regular topology creation
	Incremental design capability
Physical Awareness	Automatic timing closure assistance
Physical Awareness	Floorplan visualization
Advanced Scalability	NIU tiling	with XL option	with XL option
	Mesh topology editor	with XL option	with XL option
	Write broadcast stations	with XL option	with XL option
	Virtual channel links	with XL option	with XL option
	Source synchronous asynchronous bridges	with XL option	with XL option
	Up to 1024 bits data bus	with XL option	with XL option
	512 pending transaction support	with XL option	with XL option
Optimizations	Optimization for performance, area and wire length
	Advanced Quality of Service (QoS)
	Power management and security
	Address and data protection schemes
	Advanced in-circuit debug features
	Multi-cycle SRAM support
	Floorplan visualization
Add-on Options	Memory Re-order Buffer option
	Reliability option
	Safety (up to ISO 26262 ASIL D) option
	Advanced Scalability (XL) option
Markets	Automotive, Communications, Consumer Electronics, Enterprise Computing and Industrial Markets

FlexNoC Product Options

Seamlessly integrated extensions to the base FlexNoC feature set

Option

Large Systems: XL Option

NIU tiling
Mesh topology editor
Up to 1024 bits data bus
Virtual channel links
Write broadcast stations

Learn more about product

Option

Resilience: Safety Option

ISO 26262 Functional Safety (FuSa)
Multi-ASIL support
Interconnect-wide ECC support

Learn more about product

Option

Performance: Reorder Buffer Option

Single and Multi-channel reorder buffers (ROB):

Avoid ordering rule blocks
Avoid response serialization bottlenecks
Allow concurrent memory channel reads

Learn more about product

Customer Testimonials

Trusted by innovative
 companies everywhere

Sondrel has deployed Arteris FlexNoC interconnect IP across several customer SoC projects to great effect. Physical constraints have always been an important issue and are even more important below 16nm geometries. The latest FlexNoC 5 with its physical awareness technology, enables our RTL teams to verify that architectures meet physical constraints and provide a better starting point for our place and route team. We look forward to our continued cooperation with Arteris.

Using Arteris FlexNoC allows us to reduce development time and manage project risk. FlexNoC’s advanced quality-of-service and debugging features, combined with its multi-protocol support, allow Samsung SUHD TVs to reduce power consumption and die area for complex chips with more than 100 IP interfaces.

FlexNoC interconnect IP allowed us to dramatically increase MCU performance and functionality with no impact on die area while significantly decreasing power consumption.

As a result of our thorough evaluation, we know the Arteris FlexNoC interconnect IP will help us shorten development schedules and increase product performance, while simultaneously decreasing costs due to back-end wire routing congestion and timing closure issues.

By incorporating Arteris FlexNoC interconnect IP into our development programs, we are able to streamline our overall design time. This solution also provides us with flexibility to create derivations of our offerings to quickly adapt to changing market needs.

TSMC chose to work with Arteris on the interposer based test chip program because its interconnect technology is ideally suited to addressing the SoC wire routing congestion and timing closure challenges. TSMC and Arteris are working together to make it easier for our joint customers to adopt these technologies.

Our successful adoption of Arteris FlexNoC fabric IP has been straightforward, allowing us to more quickly architect and implement sophisticated systems-on-chip in less time and with better power consumption and performance.