Physically Aware Network-on-Chip IP
The world’s #1 on-chip fabric is used by the world’s top semiconductor design teams as the backbone on-chip communications for chips targeting the fastest growing markets.
The latest generation FlexNoC Interconnect with its integrated physical awareness technology, gives place and route teams a much better starting point while simultaneously reducing interconnect area and power consumption. FlexNoC delivers up to 5X shorter turn-around-time versus manual physical iterations.
The combined use of FlexNoC and Ncore IP in an ASIC design delivers unparalleled performance optimization, scalability, and system integration, enabling robust cache coherence, efficient communication, and flexibility, leading to market differentiation and accelerated time-to-market.
Everything design teams need to create the world’s best SoCs, faster
FlexNoC is generated from simple elementary components which are combined by a powerful set of underlying algorithms and an intuitive GUI, making it possible to build any topology.
FlexNoC easily supports long cross-chip paths by leveraging source-synchronous communications and virtual channels.
FlexNoC drives performant on-chip data flow and access to off-chip memory by enabling multi-channel HBMx memory and high bandwidth data paths.
Explore additional features of FlexNoC, download the datasheet.
NoC tiling with mesh topology for NPUs, GPUs, TPUs with FlexNoC. Up to 1024 tiles.
Create modular, scalable designs, enabling faster integration, verification and optimization.
Arteris CodaCache® last-level cache:
Automated flow to leverage SoC connectivity information:
Using built-in NoC performance analysis exploration tools
Advanced power management through clock gating, DVFS and GALS
Fewer wires using optimal NoC transport layer
Early physical awareness for faster convergence without re-designs
Through the intuitive FlexNoC UI
Saving hundreds of hours of work versus manual verification test benches
Fewer iteration loops
Reduced TTM from FlexNoC design efficiency savings
Category | Features | FlexWay | FlexNoC | FlexGen |
---|---|---|---|---|
Target Audience and Scale | Smaller-scale MCU SoCs | |||
Small-medium scale SoCs | ||||
Large scale SoCs | ||||
Instances Per Design | Single NoC instance | |||
Multiple NoC instances | ||||
Network Interface Units (NIUs) | Up to 50 NIUs | |||
Up to 200 NIUs | ||||
Up to 1000 NIUs | with XL option | with XL option | ||
Compatibility | AXI, AHB, APB, OCP, PIF, AMBA5 | |||
ACE-Lite | ||||
Smart NoC Automation | Topology generation with minimum wire length | |||
Scripting-driven regular topology creation | ||||
Incremental design capability | ||||
Physical Awareness | Automatic timing closure assistance | |||
Floorplan visualization | ||||
Advanced Scalability | NIU tiling | with XL option | with XL option | |
Mesh topology editor | with XL option | with XL option | ||
Write broadcast stations | with XL option | with XL option | ||
Virtual channel links | with XL option | with XL option | ||
Source synchronous asynchronous bridges | with XL option | with XL option | ||
Up to 1024 bits data bus | with XL option | with XL option | ||
512 pending transaction support | with XL option | with XL option | ||
Optimizations | Optimization for performance, area and wire length | |||
Advanced Quality of Service (QoS) | ||||
Power management and security | ||||
Address and data protection schemes | ||||
Advanced in-circuit debug features | ||||
Multi-cycle SRAM support | ||||
Floorplan visualization | ||||
Add-on Options | Memory Re-order Buffer option | |||
Reliability option | ||||
Safety (up to ISO 26262 ASIL D) option | ||||
Advanced Scalability (XL) option | ||||
Markets | Automotive, Communications, Consumer Electronics, Enterprise Computing and Industrial Markets |
Seamlessly integrated extensions to the base FlexNoC feature set
Single and Multi-channel reorder buffers (ROB):
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