Multi-die designs for AI innovation and performance
Upgrade your data transport from networks-on-chips (NoCs) to super-NoCs, distributed across multiple chiplets.
Overview
Optimize data flow between chiplets
Multi-die systems and chiplet-based designs are helping to push Moore’s Law into the “More-than-Moore” era as traditional monolithic chips can no longer satisfy the escalating demands of today’s complex, high-performance computing and AI workloads.
Arteris accelerates AI-driven silicon innovation with an expanded multi-die solution. Built on silicon-proven NoC technology and Magillem™ automation, the multi-die platform delivers:
- Flexible design scalability
- Differentiated AI performance
- Alignment with evolving industry standards
Working with industry standards such as Arm AMBA AXI and CXS, and with ecosystem partners that supply die-to-die controllers and PHYs , whether Universal Chiplet Interconnect Express™ (UCIe), Bunch of Wires (BoW) or proprietary links, Arteris NoC IP helps ensure seamless, low-latency data flow between chiplets. As a result, developers can hit aggressive performance, power and time-to-market goals, despite the growing complexity of multi-die designs.
Advantages
Designed for interoperability and performance
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Interoperability
Connect to industry-leading die-to-die PHY connections with their digital controllers using standard interfaces like Arm AMBA protocols.
Bandwidth
Increase on-chip and off-chip bandwidth with HBM2 and multichannel memory support, multicast/broadcast writes, VC-Link™ Virtual Channels, and source-synchronous communications.
Low power
Fewer wires and fewer gates consume less power, breaking communication paths into smaller segments. This controls power to only active segments, and simple internal protocols allow aggressive clock gating.
Multi-Die Use-Cases
Homogeneous Scale-Out
Demand for larger, scalable systems is driving the requirement for homogeneous solutions which enable a single chiplet design to be re-used multiple times to scale up to a larger system. A homogeneous chiplet solution can help where the design is too large for a reticle (858 mm2) or yield issues would make a single die solution prohibitively expensive compared with multiple smaller dies with improved yield.
Heterogeneous Disaggregation
Heterogeneous disaggregation is a chiplet solution where the individual dies differ. The design may be too large for a single die, either due to reticle limits or yield, similar to heterogenous solutions. Multiple dies can also facilitate the most appropriate semiconductor process for the application. For example, SRAM scaling has slowed since the 7 nm node and SRAM in 3 nm is no smaller than 5 nm. If a die contains large amounts of SRAM, implementing the SRAM on a lower cost, more mature process with a higher yield may be a better alternative. Likewise, specialist I/O (eg, high voltage) or RF may drive the solution towards a separate I/O chiplet.
Standards
Standards collaboration across the industry
Choosing the proper NoC protocol for die-to-die data transport is critical to meeting performance, latency, and power requirements in system design. Providers of the physical connections typically deliver PHYs and controllers, including link layers that carry the raw flow control units (FLITs) from die to die.
Arteris works with partners that include Synopsys, Cadence, Alphawave, Blue Cheetah Analog, Innosilicon, and others to align on NoC to controller/PHY interfaces. In addition, Arteris actively participates in related standardization efforts, including:
Advanced Microcontroller Bus Architecture
Compute Express Link
Bunch of Wires
Peripheral Component Interconnect Express
Universal Chiplet Interface
Products for multi-die designs
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As Al pushes the limits of performance and power efficiency, monolithic SoCs with chiplet capabilities have become essential in delivering the integration and scalability that traditional SoC designs can't match. Arteris technology plays a key role in realizing this vision by providing the underlying connectivity in our 5th generation R-Car automotive silicon and driving the new era of automotive innovation.
AMD is driving innovations that scale AI from cloud to client by continually developing leadership computing technologies and best-in-class IP. Integrating Arteris’ FlexGen NoC IP technology into a range of AMD chiplets, we can automate interconnect configuration and enable seamless connectivity among SoC components while strengthening the best end-to-end AI compute portfolio in the industry.
Rebellions have utilized Arteris interconnect IP and SoC integration software in select products to support performance optimization and efficient integration across our Al accelerator development efforts. Arteris FlexNoC interconnect IP and Magillem software have contributed to our design workflows, aligning with our focus on modular and scalable Al system architectures.
We continue to leverage Arteris' network-on-chip IP products in our designs as we drive the next wave of advancements in Al computing.
Arteris is a proven technology partner
- their FlexNoC IP provides superior performance for our next-generation
Al compute.
Arteris' technology allows us to achieve the performance and area targets we need for our MOSAICS-LP platform. The proven capabilities of Arteris' network-on-chip IP ensure efficient scaling of our solutions while streamlining our design process.
Case Studies
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Quick Reference Guides
What's New
Latest news
Blog
Semiconductor Engineering: AI Energy Gap and Chiplets: Why Data Movement Matters
At the panel discussion at Chiplet Summit 2026, where Arteris was among the experts, participants emphasized that efficient AI chiplets require more than fast physical links like UCIe—they demand smart, system-level architecture around data movement, coherency, and protocol choice. As
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Blog
Electronic Design: Bridging the Gap to Chiplet Interoperability
This article examines the gap between today’s tightly managed multi-die implementations and the long-term vision of true multi-vendor chiplet interoperability. It explains how companies are deploying homogeneous and heterogeneous architectures, why proprietary flows still limit plug-and-play integration, and how standards
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Press Releases
Arteris Network-on-Chip Technology Achieves Deployment Milestone of 4 Billion Chips and Chiplets
Arteris network-on-chip interconnect IP ships in production silicon at accelerating scale across AI-driven automotive, enterprise computing, consumer electronics, industrial and other applications.
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Blog
EE Times: The Data Dilemma: Cracking the Code of Data Movement for the Next Wave of Semiconductor Innovation
As semiconductor architectures scale toward chiplets, multi-die SoCs, and AI-driven workloads, data movement—not raw compute—has emerged as the primary limiter of performance, power, and scalability. The article argues that network-on-chip fabrics are becoming the true center of gravity in modern
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Blog
2026 Predictions: System-Level Design, AI-Native Workflows, and the Rise of Multi-Die Compute Fabrics
Explore 2026 semiconductor predictions as AI accelerates system-level design, multi-die compute fabrics, chiplets, 2.5D/3D integration, and AI-native architecture workflows reshape how advanced systems are built and verified.
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Press Releases
Arteris Closes Acquisition of Cycuity
Arteris closes acquisition of Cycuity, adding leading semiconductor cybersecurity assurance technology to product portfolio.
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Blog
Advancing Europe’s Automotive Chiplet Vision: Arteris Joins CHASSIS to Accelerate Software-Defined Mobility
Arteris joins CHASSIS, Europe’s open automotive chiplet initiative with advanced NoC and multi-die interconnect technology that accelerates software-defined mobility.
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Press Releases
Arteris to Expand Portfolio with Acquisition of Cycuity, a Leader in Semiconductor Cybersecurity Assurance
Arteris has entered into a definitive agreement to acquire Cycuity, Inc., a leading provider of semiconductor cybersecurity assurance. This pending acquisition will enable Arteris' customers to achieve secure on-chip data movement. Learn more in the press release.
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Blog
Semiconductor Engineering: Efficiency Defines The Future Of Data Movement
As AI workloads expand and chiplet architectures evolve, data movement now consumes more energy than computation itself. Achieving higher performance within fixed power budgets demands efficient, intelligent interconnects and automation across multi-die SoC designs. Learn more in the article.
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Press Releases
Arteris Selected by 2V Systems for IO Chiplet for Data Center
Arteris selected by 2V Systems for IO chiplet for data center. Arteris’ network-on-chip IP technology enables high-bandwidth, low latency data movement for AI workloads.
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Blog
EE Times: A Guide to Building Chiplets Today While Shaping Tomorrow’s Standards
Chiplet standards like UCIe, AIB, and BoW are still evolving, but design teams can start building with chiplets today by adopting packaging automation, structured IP metadata, and scalable interconnect fabrics that enable flexibility and future-proof integration. Learn how to design
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Blog
Semiconductor Engineering: The Future Of SoC Design Is Data Movement
The semiconductor industry is shifting from focusing on raw compute to tackling the growing challenge of data movement in complex SoCs. With advances in chiplets, high-bandwidth memory, CXL fabrics, and automotive zonal architectures, predictable performance now depends on layered, automated,
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