Home » Resources

Resources

Case Studies

Menta Case Study

Scalable Network-on-Chip Enables a Modular Chiplet Platform

Menta is bringing its embedded FPGA leadership into the chiplet era with the MOSAICS Chiplet Platform, enabling modular, domain-specific silicon with faster time-to-market and lower system cost. FlexNoC interconnect IP serves as the scalable communications backbone of the MOSAICS Hub, providing predictable, high-performance data movement across heterogeneous chiplets and supporting multiple platform configurations and generations.

learn more about case study

Tenstorrent Case Study

Cache Coherent and Non-Coherent NoCs Connect AI and HPC SoCs and Chiplets

Tenstorrent has emerged as a key player in the AI hardware landscape, with a mission to build compute solutions that are scalable, flexible, and future-ready. They set out to build "computers for AI" aimed at delivering unprecedented performance, scalability, and flexibility across applications including HPC/AI, automotive, and robotics. FlexNoC fully addressed Tenstorrent’s non-coherent NoC requirements in its current generation of chiplets. Ncore addressed Tenstorrent’s cache coherent NoC requirements in next generation of chiplets in planning.

learn more about case study

SCALINX Case Study

Combination of Coherent and Non-Coherent NoCs Facilitates Cutting-Edge SoC Design

SCALINX, a fabless semiconductor company specializing in the design of system-on-chip (SoC) devices, was looking to develop a large, next-generation SoC integrating analog, digital, mixed-signal, and RF functionality. With Arteris, they completed the bulk of the frontend design in 1.5 years.

learn more about case study

SiMa.ai Case Study

Push-Button Ease of Arteris FlexNoC Freed Up the Team to Focus on Designing The World’s First Machine Learning SoC

SiMa.ai was looking to design a state-of-the-art machine learning accelerator (MLA) and they needed an easy way to generate a NoC quickly. Using Arteris, they saved years on their project timeline.

learn more about case study

Dream Chip Case Study

Use of NoC IP Facilitates Tailoring SoC Platform Design into Bespoke SoC Devices

Dream Chip Technologies set out to create an optimized SoC foundation to support custom designs for next-gen automotive machine vision applications. FlexNoC’s configurability, functional safety option, and ease of use saved time and money, allowing the team to address unique requirements.

learn more about case study

Aion Silicon Case Study

Shortening Leading-Edge ADAS Design Cycles With FlexNoC To Deliver Customer Success

Aion Silicon delivered implementation-ready RTL based on client concepts reducing design time from 4-5 months down to 1-2 months on advanced ADAS SoC designs using Arteris.

learn more about case study

Datasheets

Infographics

Podcasts

Podcast

EE Times: When AI Meets Hardware Security

Sally Ward-Foxton speaks with Arteris’ Andreas Kuehlmann about the uGen framework’s recreation of a Spectre-v1 proof of concept, why hardware vulnerabilities are especially costly to fix after fabrication, and why AI chips may represent the next frontier in cybersecurity.

Learn more about podcast

Podcast

EE Journal: Securing the Silicon: The Seismic Shift to Hardware Security

Amelia Dalton of EE Journal and Jason Oberg of Arteris explore how Cycuity’s integration into Arteris is changing the game for system-level security and discuss how teams can address the emerging risks in our era of distributed systems, chiplets, and constant data movement.

Learn more about podcast

Podcast

SemiWiki: The Growing Threat of Hardware Security Breaches and What to do About it with Dr. Andreas Kuehlmann

Daniel Nenni of SemiWiki talks with Dr. Andreas Kuehlmann of Arteris about AI-driven cyberattacks, rising hardware security threats, regulation, and how to prepare.

Learn more about podcast

Podcast

Inside Chips Podcast: Data Movement in the AI Age with Charlie Janac

AI is reshaping the chip industry — but the real challenge isn’t just compute, it’s data movement and power efficiency. In this episode, Ed Sperling (Semiconductor Engineering) talks with Charlie Janac (President & CEO of Arteris) about why networks-on-chip are critical for effective data movement, how chiplets change system design,

Learn more about podcast

Presentations

Presentation

Will it Blend? – Verifying the Hardware / Software Interface of Complex SoCs

This presentation highlights how Arteris SoC integration automation technologies streamline the blend of hardware, software, and verification components including VHDL, SystemVerilog, UPF, IP-XACT, and UVM to boost productivity and enable first-time silicon success.

Learn more about presentation

Presentation

Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip (SoCs)

Presented at IQPC Application of ISO 26262 2022 Conference, describes an approach that uses a hierarchal and modular library of safety components to describe failure modes, safety mechanism diagnostic coverage, and other functional safety metrics at a level that scales with the size and complexity of an SoC and enables

Learn more about presentation

Presentation

Building Better IP with RTL Architect NoC IP Physical Exploration

Voted one of the “Top Ten Best Presentations” at SNUG Silicon Valley 2023, this presentation discusses the importance of NoCs and their impact on timing analysis and power consumption. It introduces a flow and methodology that utilizes RTL-based estimation of timing and power consumption using RTL Architect in conjunction with

Learn more about presentation

Presentation

Efficient Scaling of AI Accelerators Using NoC Tiling

Learn about the benefits of using NoC tiling in AI accelerators, seamless data management with NoC solutions and real-world applications for AI vision.

Network-on-Chip (NoC)

Learn more about presentation

Presentation

FMEDA Automation for Scalability and Reuse in Complex Systems on Chips (SoCs)

Failure modes, effects, and diagnostic analysis (FMEDA) for sophisticated chips with hundreds of IP blocks are fraught with complexity and opportunities for systematic errors. This presentation will describe an approach that uses a hierarchal and modular library of safety components to describe failure modes, safety mechanism diagnostic coverage, and other

Learn more about presentation

Quick Reference Guides

EU CRA Hardware Readiness Guide

Twelve practical questions to help semiconductor teams understand where they stand, prepare customer-ready security evidence, and plan for EU Cyber Resilience Act requirements.

Learn more about product

Quick Reference Guides

Hardware Security Assurance Checklist

This hardware security checklist helps engineering teams evaluate the maturity of their hardware security practices across the entire development lifecycle.

Learn more about product

Solution Briefs

Solution Brief

Accelerate, Derisk, and Secure RISC-V-based SoC Designs with Arteris

Connect RISC-V computing and accelerate subsystems with silicon-proven interconnect IP. Unify protocols such as AMBA across 100’s of re-used IP blocks cutting complexity and maximizing resource efficiency. Derisk project schedules with leading system IP and expert support.

Learn more about solution briefs

Solution Brief

Accelerate, Optimize, and Secure AI-Based SoC Designs with Arteris

Optimize performance, power, and area for AI-driven SoCs from data centers to edge devices. Enable faster innovation in generative AI, physical AI, and autonomous systems with proven Arteris technology built for scalability, efficiency, and hardware assurance.

Learn more about solution briefs

White Papers

White Paper

Assuring Comprehensive Security Coverage in Hardware Design

Is your hardware design prepared to withstand today’s complex threat landscape? Verifying the effectiveness of security functionality and protections is essential to safeguarding your designs. By adopting a systematic framework and measuring coverage throughout the pre-silicon development cycle, you can proactively identify vulnerabilities and strengthen your hardware’s resilience.

Learn more about paper

White Paper

Build Secure SoCs from the Start

This eBook examines the hardware security assurance in modern semiconductor design. Discover how to detect vulnerabilities early in the development lifecycle, reduce costly silicon respins, and deliver secure silicon products with greater confidence.

Learn more about paper

White Paper

Making Cache Coherent SoC Design Easier with Ncore™

As the number and variety of computing elements in SoCs grow, specific application areas require the tight connection of key processing elements through coherency. Ncore Interconnect IP from Arteris makes cache coherent SoC designs easier, saving 100’s of person-years effort per project vs DIY solutions.

Learn more about paper

Videos

#AIInfraSummit26: Performance at Scale, Energy Efficiency & Cybersecurity

Michal Siwinski, EVP, Chief Product and Marketing Officer, GM Security Solutions at Arteris, discusses the critical trends shaping AI infrastructure at the AI Infra Summit. Siwinski identifies three major themes dominating the industry conversation: performance at scale, energy efficiency, and cybersecurity. He explores how chiplet architectures are enabling massive compute scaling, why energy-efficient design must start at the silicon level, and how the semiconductor attack surface has expanded dramatically since early processor vulnerabilities like Spectre and Meltdown. Siwinski explains why securing AI infrastructure requires a comprehensive approach that begins with the underlying silicon components.

Learn more about video

Interview with Aniket Saha, VP of Product Management, Tenstorrent

Discover how Tenstorrent is using Arteris Network-on-Chip (NoC) IP to power the next generation of AI compute. In this interview, Aniket Saha, VP of Product Management, Tenstorrent, shares how Arteris silicon-proven NoC technology helped solve complex data movement challenges while providing the flexibility needed for future innovation.

Learn more about video

Webinars

Webinar

Revolutionizing SoC Performance with Network-on-Chip Technology

See how you can create NoCs with less wires, more bandwidth, smaller area with incredible efficiency, flexibility and scalability to achieve your SoC goals.

Learn more about webinar

Popup Overlay

Resources

Case Studies

Datasheets

Infographics

Accelerating Timing Closure for Networks-on-Chip (NoCs) With Physical Awareness

Simplifying SoC Integration with Arteris

Podcasts

EE Times: When AI Meets Hardware Security

EE Journal: Securing the Silicon: The Seismic Shift to Hardware Security

SemiWiki: The Growing Threat of Hardware Security Breaches and What to do About it with Dr. Andreas Kuehlmann

Inside Chips Podcast: Data Movement in the AI Age with Charlie Janac

SemiWiki: How NoC Tiling Capability is Changing the Game for AI Development with Andy Nightingale

EE Times: Automating NoC Design Masters SoC Complexity

Presentations

The Road to Chiplet Scalability 2026

Will it Blend? – Verifying the Hardware / Software Interface of Complex SoCs

Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip (SoCs)

Building Better IP with RTL Architect NoC IP Physical Exploration

Efficient Scaling of AI Accelerators Using NoC Tiling

FMEDA Automation for Scalability and Reuse in Complex Systems on Chips (SoCs)

Quick Reference Guides

7 Game-Changing Benefits of Arteris Multi-Die Solutions for AI-Driven Silicon Innovation

EU CRA Hardware Readiness Guide

Hardware Security Assurance Checklist

10 Key FlexGen Interconnect Advantages for Faster, Smarter SoC Design

7 Powerful Features of Magillem Connectivity that Streamline SoC Design

7 Ways Magillem Registers Streamlines Hardware-Software Interface Design

Solution Briefs

White Papers

Assuring Comprehensive Security Coverage in Hardware Design

Build Secure SoCs from the Start

Enabling Comprehensive CWE-based Assurance for RISC-V Processor

Boost SoC Efficiency and Speed with FlexGen Smart NoC IP Automation White Paper

Making Cache Coherent SoC Design Easier with Ncore™

Making SoC Integration Simple – Achieve Higher Productivity and Quality

Videos

#AIInfraSummit26: Performance at Scale, Energy Efficiency & Cybersecurity

Hardware Security Assurance from Arteris | Know Where Your Assets Really Go

CodaCache® from Arteris – Ensure smooth data movement in modern SoC designs

Interview with Drew Barbier, VP of IP Business Unit, MIPS

Interview with Aniket Saha, VP of Product Management, Tenstorrent

Panel with Arteris, GF & Tenstorrent: RISC-V Ecosystem Growth for Physical AI

Webinars

Considerations When Architecting Your Next SoC: NoC

Making Automotive Semiconductor Cybersecurity Practical

Accelerate Time To Market With a First-Time Right Process

Arteris FlexNoC 5 – Industry’s First Physically Aware Network-on-Chip IP

How to Achieve Efficient Communication and Data Sharing in Multi-Core SoC Designs

Revolutionizing SoC Performance with Network-on-Chip Technology