Home » Resources

Resources

Case Studies

Tenstorrent Case Study

Cache Coherent and Non-Coherent NoCs Connect AI and HPC SoCs and Chiplets

Tenstorrent has emerged as a key player in the AI hardware landscape, with a mission to build compute solutions that are scalable, flexible, and future-ready. They set out to build "computers for AI" aimed at delivering unprecedented performance, scalability, and flexibility across applications including HPC/AI, automotive, and robotics. FlexNoC fully addressed Tenstorrent’s non-coherent NoC requirements in its current generation of chiplets. Ncore addressed Tenstorrent’s cache coherent NoC requirements in next generation of chiplets in planning.

learn more about case study

SCALINX Case Study

Combination of Coherent and Non-Coherent NoCs Facilitates Cutting-Edge SoC Design

SCALINX, a fabless semiconductor company specializing in the design of system-on-chip (SoC) devices, was looking to develop a large, next-generation SoC integrating analog, digital, mixed-signal, and RF functionality. With Arteris, they completed the bulk of the frontend design in 1.5 years.

learn more about case study

SiMa.ai Case Study

Push-Button Ease of Arteris FlexNoC Freed Up the Team to Focus on Designing The World’s First Machine Learning SoC

SiMa.ai was looking to design a state-of-the-art machine learning accelerator (MLA) and they needed an easy way to generate a NoC quickly. Using Arteris, they saved years on their project timeline.

learn more about case study

Dream Chip Case Study

Use of NoC IP Facilitates Tailoring SoC Platform Design into Bespoke SoC Devices

Dream Chip Technologies set out to create an optimized SoC foundation to support custom designs for next-gen automotive machine vision applications. FlexNoC’s configurability, functional safety option, and ease of use saved time and money, allowing the team to address unique requirements.

learn more about case study

Aion Silicon Case Study

Shortening Leading-Edge ADAS Design Cycles With FlexNoC To Deliver Customer Success

Aion Silicon delivered implementation-ready RTL based on client concepts reducing design time from 4-5 months down to 1-2 months on advanced ADAS SoC designs using Arteris.

learn more about case study

Inuitive Case Study

Innovative NoC Implementation Dramatically Speeds Derivative Design

Inuitive, a fabless semiconductor company, created a new iteration of an existing vision-on-chip device quickly and easily, meeting an aggressively short time-to-market schedule using Arteris interconnect IP.

learn more about case study

Datasheets

Infographics

Podcasts

Podcast

Inside Chips Podcast: Data Movement in the AI Age with Charlie Janac

AI is reshaping the chip industry — but the real challenge isn’t just compute, it’s data movement and power efficiency. In this episode, Ed Sperling (Semiconductor Engineering) talks with Charlie Janac (President & CEO of Arteris) about why networks-on-chip are critical for effective data movement, how chiplets change system design,

Learn more about podcast

Podcast

EE Journal: Managing the Massive Data Throughput: AI-Based Designs and The Value of NoC Tiling

In this podcast with Amelia Dalton and Andy Nightingale, explore the key challenge faced by SoC designers when building NoC interconnects for AI-based designs, the details of NoC interconnect IP soft tiling, and some real-world examples of AI-based designs that benefit from NoC IP soft tiling.

Learn more about podcast

Podcast

EE Journal: The Freedom to Innovate: Arteris and the Rise of RISC-V

The adoption of RISC-V is spreading. Versatility and “freedom to innovate” are powering the ecosystem. Frank Schirrmeister, VP Solutions and Business Development at Arteris, spoke to EE Journal’s Amelia Dalton on the fish fry podcast.

Learn more about podcast

Podcast

EE Journal: The Network-on-Chip Pioneer: How Arteris Enabling SoC Developers to Create Physically Valid NoCs Faster

Physically aware network-on-chips take center stage in this week’s Fish Fry podcast! Andy Nightingale from Arteris and I investigate the role that network-on-chips have played in the development of SoC designs.

Learn more about podcast

Presentations

Presentation

Will it Blend? – Verifying the Hardware / Software Interface of Complex SoCs

This presentation highlights how Arteris SoC integration automation technologies streamline the blend of hardware, software, and verification components including VHDL, SystemVerilog, UPF, IP-XACT, and UVM to boost productivity and enable first-time silicon success.

Learn more about presentation

Presentation

Architecting the Future of Deep Learning Presentation

Learn about the history of artificial intelligence (AI), machine learning, (ML), and deep learning. Keynote presentation at the 2018 eSilicon “ASICs Unlock Deep Learning Innovation” seminar.

Learn more about presentation

Presentation

Arm & Arteris AI and ISO 26262 Presentation

Arm & Arteris joint presentation from ICCAD China 2018 describes how new artificial (AI) and machine learning (ML) acceleration IP from Arm, like the Arm® NPU and Mali™ C71, can be implemented in ISO 26262-compliant automotive systems with the help of functional safety mechanisms in the Arteris FlexNoC and Ncore

Learn more about presentation

Presentation

Arm TechCon: Implementing ISO 26262 Compliant AI Systems-on-Chip with Arm and Arteris

Arm, Arteris, and Dream Chip Technologies joint presentation from Arm TechCon 2019 explains IP integration requirements for AI subsystems in ISO 26262-compliant chips. With an emphasis on techniques and safety mechanisms to enhance the diagnostic coverage of SoCs integrating an NPU and Safety Island. Topic areas include system design to

Learn more about presentation

Presentation

Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip (SoCs)

Presented at IQPC Application of ISO 26262 2022 Conference, describes an approach that uses a hierarchal and modular library of safety components to describe failure modes, safety mechanism diagnostic coverage, and other functional safety metrics at a level that scales with the size and complexity of an SoC and enables

Learn more about presentation

Presentation

Building Better IP with RTL Architect NoC IP Physical Exploration

Voted one of the “Top Ten Best Presentations” at SNUG Silicon Valley 2023, this presentation discusses the importance of NoCs and their impact on timing analysis and power consumption. It introduces a flow and methodology that utilizes RTL-based estimation of timing and power consumption using RTL Architect in conjunction with

Learn more about presentation

Solution Briefs

Solution Brief

Accelerate and Derisk RISC-V-based SoC Designs with Arteris

Connect RISC-V computing and accelerate subsystems with silicon-proven interconnect IP. Unify protocols such as AMBA across 100’s of re-used IP blocks cutting complexity and maximizing resource efficiency. Derisk project schedules with leading system IP and expert support.

Learn more about solution briefs

Solution Brief

Accelerate and Optimize AI-Based SoC Designs with Arteris

Accelerate AI chip design with intelligent interconnect and system IP. Optimize performance, power, and area for AI-driven SoCs from data centers to edge devices. Enable faster innovation in generative AI, robotics, and autonomous systems with proven Arteris technology built for scalability and efficiency.

Learn more about solution briefs

Solution Brief

Accelerate AI-Driven Silicon Innovation with Arteris Multi-Die Solution

The Arteris Multi-Die Solution delivers flexible design scalability for chiplet-based systems, optimal PPA, highest quality-of-results (QoR), functional safety and broad standards support to achieve the fastest time to silicon.

Learn more about solution briefs

White Papers

White Paper

Making Cache Coherent SoC Design Easier with Ncore

As the number and variety of computing elements in SoCs grow, specific application areas require the tight connection of key processing elements through coherency. Ncore Interconnect IP from Arteris makes cache coherent SoC designs easier, saving 100’s of person-years effort per project vs DIY solutions.

Learn more about paper

White Paper

A Configurable Test Infrastructure using a Mixed-Language and Mixed-Level IP Integration IP-XACT Flow

This paper written with NXP describes an efficient integration flow for mixed-language and mixed-abstraction level IPs through IP-XACT flow automation.

Learn more about paper

White Paper

A Design Flow for Critical Embedded Systems

In this paper by Airbus, Thales, STMicroelectronics, Arteris and other, learn how IP encapsulation/packaging and interoperability using IP-XACT enabled automation in a complex verification & validation flow for aeronautical systems.

Learn more about paper

White Paper

A Power Consumption Estimation Approach for Embedded Software Design using Trace Analysis

This paper presents a lightweight and cost-effective approach to power estimation suitable for software developers. It relies on trace analysis and high-level modeling of architectures to perform quick and efficient power consumption estimations without losing accuracy.

Learn more about paper

Videos

Interview

Interview with Andy Bond, Silicon Verification Director, Axelera AI

Axelera AI is bringing high-performance AI to the edge with low-power, purpose-built hardware for applications ranging from automation and robotics to industrial vision and smart security. In this interview, Andy Bond, Director of Verification, shares how the company approaches edge inference and the opportunities and challenges of deploying AI across diverse real-world use cases. Watch to hear how their team is shaping the next generation of edge AI.

Learn more about video

Presentation

Smart NoC Automation: Accelerating AI-Ready SoC Design in the Era of Chiplet

Explore how smart NoC generation can help optimize your NoC design processes by reducing iterations and bringing unprecedented quality of results.

Learn more about video

intro video

Magillem Connectivity from Arteris – Accelerate the Design of Complex SoCs

Magillem Connectivity enables design teams to automate and streamline SoC assembly, accelerating development while maintaining the highest quality standards.

Learn more about video

intro video

FlexNoC 5 Physically Aware Network-on-Chip IP

FlexNoC 5 physically aware network-on-chip IP incorporates physical constraint management across power, performance, and area (PPA). Get up to 5X faster physical convergence vs manual physical iterations and achieve PPA goals within schedule and budget constraints.

Learn more about video

intro video

Magillem Registers – Automate the Hardware/Software Interface for Fast Chip Design

Magillem Registers is a comprehensive register design and management technology that accurately automates the hardware/software interface (HSI) to quickly develop chips and chiplets ranging from IoT devices to complex AI datacenter multi-die SoCs.

Learn more about video

Webinars

Webinar

Revolutionizing SoC Performance with Network-on-Chip Technology

See how you can create NoCs with less wires, more bandwidth, smaller area with incredible efficiency, flexibility and scalability to achieve your SoC goals.

Learn more about webinar

Webinar

Three Perspectives on System Design Challenges

Explore the positive impact a single source of truth environment can have on the different teams involved in a SOC design and what it means to quickly enable consistent HSI output generation throughout an entire system design. Download the webinar and learn how to increase productivity and reduce risk to get to market faster with a proven, best-in-class approach that saves time and money.

Learn more about webinar

Popup Overlay

Resources

Case Studies

Datasheets

Infographics

Accelerating Timing Closure for Networks-on-Chip (NoCs) With Physical Awareness

Simplifying SoC Integration with Arteris

Podcasts

Inside Chips Podcast: Data Movement in the AI Age with Charlie Janac

SemiWiki: How NoC Tiling Capability is Changing the Game for AI Development with Andy Nightingale

EE Times: Automating NoC Design Masters SoC Complexity

EE Journal: Managing the Massive Data Throughput: AI-Based Designs and The Value of NoC Tiling

EE Journal: The Freedom to Innovate: Arteris and the Rise of RISC-V

EE Journal: The Network-on-Chip Pioneer: How Arteris Enabling SoC Developers to Create Physically Valid NoCs Faster

Presentations

Will it Blend? – Verifying the Hardware / Software Interface of Complex SoCs

Architecting the Future of Deep Learning Presentation

Arm & Arteris AI and ISO 26262 Presentation

Arm TechCon: Implementing ISO 26262 Compliant AI Systems-on-Chip with Arm and Arteris

Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip (SoCs)

Building Better IP with RTL Architect NoC IP Physical Exploration

Solution Briefs

White Papers

Boost SoC Efficiency and Speed with FlexGen Smart NoC IP Automation White Paper

Making Cache Coherent SoC Design Easier with Ncore

Making SoC Integration Simple – Achieve Higher Productivity and Quality

A Configurable Test Infrastructure using a Mixed-Language and Mixed-Level IP Integration IP-XACT Flow

A Design Flow for Critical Embedded Systems

A Power Consumption Estimation Approach for Embedded Software Design using Trace Analysis

Videos

Interview with Andy Bond, Silicon Verification Director, Axelera AI

Smart NoC Automation: Accelerating AI-Ready SoC Design in the Era of Chiplet

Magillem Connectivity from Arteris – Accelerate the Design of Complex SoCs

FlexGen Smart NoC IP from Arteris Revolutionizes Complex SoC Designs

FlexNoC 5 Physically Aware Network-on-Chip IP

Magillem Registers – Automate the Hardware/Software Interface for Fast Chip Design

Webinars

Considerations When Architecting Your Next SoC: NoC

Accelerate Time To Market With a First-Time Right Process

Arteris FlexNoC 5 – Industry’s First Physically Aware Network-on-Chip IP

How to Achieve Efficient Communication and Data Sharing in Multi-Core SoC Designs

Revolutionizing SoC Performance with Network-on-Chip Technology

Three Perspectives on System Design Challenges