Resources

Case Studies

SCALINX Case Study

Combination of Coherent and Non-Coherent NoCs Facilitates Cutting-Edge SoC Design

SCALINX, a fabless semiconductor company specializing in the design of system-on-chip (SoC) devices, was looking to develop a large, next-generation SoC integrating analog, digital, mixed-signal, and RF functionality. With Arteris, they completed the bulk of the frontend design in 1.5 years.

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Dream Chip Case Study

Use of NoC IP Facilitates Tailoring SoC Platform Design into Bespoke SoC Devices

Dream Chip Technologies set out to create an optimized SoC foundation to support custom designs for next-gen automotive machine vision applications. FlexNoC’s configurability, functional safety option, and ease of use saved time and money, allowing the team to address unique requirements.

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Inuitive Case Study

Innovative NoC Implementation Dramatically Speeds Derivative Design

Inuitive, a fabless semiconductor company, created a new iteration of an existing vision-on-chip device quickly and easily, meeting an aggressively short time-to-market schedule using Arteris interconnect IP.

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SiMa.ai Case Study

Push-Button Ease of Arteris FlexNoC Freed Up the Team to Focus on Designing The World’s First Machine Learning SoC

SiMa.ai was looking to design a state-of-the-art machine learning accelerator (MLA) and they needed an easy way to generate a NoC quickly. Using Arteris, they saved years on their project timeline.

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Sondrel Case Study

Shortening Leading-Edge ADAS Design Cycles With FlexNoC To Deliver Customer Success

Sondrel delivered implementation-ready RTL based on client concepts reducing design time from 4-5 months down to 1-2 months on advanced ADAS SoC designs using Arteris.

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Datasheets

Datasheet

CodaCache™ Last-Level Cache IP Datasheet

Standalone, highly configurable last level cache
Arm® AMBA® AXI compliant
Configurable way partitioning, sizing, & scratchpad configurations

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Datasheet

CSRCompiler™ Datasheet – The HW/SW Interface Foundation for Design Innovation

Production-proven method to describe the required behaviors and implementation details of the HSI
True cross-compiler with extensive validation of input formats, verifying semantic and syntactic correctness.
Extremely fast, generates in seconds superior quality synthesizable RTL, software headers, UVM RAL, Docx/HTML documentation

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Datasheet

FlexGen™ Smart Interconnect IP Datasheet

Automated non-coherent NoC IP generation with expert results
Significantly reduces NoC development time
10x productivity boost over manual NoC flows
Wire length reduction by up to 30% and latency by up to 10%
Delivers lowest routing congestion, die area and power consumption

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Datasheet

FlexNoC 5 & FlexWay 5 Functional Safety (FuSa) Option

ISO 26262 ASIL D certifiable. Helps enable the highest level of functional safety.
Comprehensive safety features. ECC, packet consistency checkers, unit duplication, initiator timeout, FMEDA generation, and fault reporting logic BIST.
Error detection and correction. Ensure data integrity and system operation.
Fault detection and redundancy. Enhance system reliability and resilience.
Compliance with industry standards. Helps meet automotive and industrial safety requirements.
Peace of mind. Helps to ensure end-user and environmental safety.

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Datasheet

FlexNoC Reliability Option for Enterprise Applications

Enables robust reliability in enterprise SoC designs
Helps with seamless coordination of data and control signals in challenging environmental conditions
Enhanced data integrity while remaining customizable for specific enterprise applications

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Datasheet

FlexNoC Reliability Option for Industrial Applications

Enabling Long-term performance and reliability
Helps address the issues of wear, environmental threats, and stress on components
Immediate fault mitigation through robust error correction and data integrity

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Infographics

Infographic

A Single Source Unified Approach to CSR Register Development

Design teams are getting crushed by growing complexity and aggressive schedules. In this infographic, see how to streamline and accelerate SoC integration with automation, saving time and money.

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Podcasts

Podcast

EE Times: Automating NoC Design Masters SoC Complexity

In this podcast, Sally Ward-Foxton and Michal Siwinski discuss how FlexGen, smart NoC IP, is revolutionizing NoC design through automation and why this is crucial for today’s chips. How it addresses the growing demands of AI, and what the future holds for NoC technology.

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Podcast

SemiWiki: How Arteris FlexGen Smart NoC IP Democratizes Advanced Chip Design

SemiWiki’s Dan Nenni explores the capabilities and impact of Arteris FlexGen - Smart NoC IP with Rick Bye, director of Product Management and Marketing at Arteris. This revolutionary product uses cutting-edge AI heuristics and machine learning to automate NoC generation and deliver expert-level results without the expert or length design

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Podcast

EE Journal: Managing the Massive Data Throughput: AI-Based Designs and The Value of NoC Tiling

In this podcast with Amelia Dalton and Andy Nightingale, explore the key challenge faced by SoC designers when building NoC interconnects for AI-based designs, the details of NoC interconnect IP soft tiling, and some real-world examples of AI-based designs that benefit from NoC IP soft tiling.

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Podcast

Electronic Design: All About NoCs

Today’s SoCs are very complex. They have multiple cores and often these cores vary in type, e.g., CPUs, GPUs, and NPUs. Connecting these to peripherals and memory typically involves one or more network-on-chips (NoCs). In this podcast, Electronic Design Editor Bill Wong talks with Andy Nightingale, VP Product Management and

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Podcast

SemiWiki: The Impact of Arteris on Automotive and Beyond with Frank Schirrmeister

Dan Nenni of SemiWiki is joined by Arteris’ Frank Schirrmeister in a conversation on automotive and the impact of network-on-chip IP on system design.

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Podcast

SemiWiki: A Broad View of Design Architectures and the Role of the NoC with Arteris’ Michal Siwinski

SemiWiki’s Dan Nenni welcomes Michal Siwinski, CMO of Arteris, for an in-depth discussion of modern design architectures and the crucial role of Network-on-Chips (NoCs).

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Presentations

Presentation

Architecting the Future of Deep Learning Presentation

Learn about the history of artificial intelligence (AI), machine learning, (ML), and deep learning. Keynote presentation at the 2018 eSilicon “ASICs Unlock Deep Learning Innovation” seminar.

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Presentation

Arm & Arteris AI and ISO 26262 Presentation

Arm & Arteris joint presentation from ICCAD China 2018 describes how new artificial (AI) and machine learning (ML) acceleration IP from Arm, like the Arm® NPU and Mali™ C71, can be implemented in ISO 26262-compliant automotive systems with the help of functional safety mechanisms in the Arteris FlexNoC and Ncore

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Presentation

Arm TechCon: Implementing ISO 26262 Compliant AI Systems-on-Chip with Arm and Arteris

Arm, Arteris, and Dream Chip Technologies joint presentation from Arm TechCon 2019 explains IP integration requirements for AI subsystems in ISO 26262-compliant chips. With an emphasis on techniques and safety mechanisms to enhance the diagnostic coverage of SoCs integrating an NPU and Safety Island. Topic areas include system design to

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Presentation

Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip (SoCs)

Presented at IQPC Application of ISO 26262 2022 Conference, describes an approach that uses a hierarchal and modular library of safety components to describe failure modes, safety mechanism diagnostic coverage, and other functional safety metrics at a level that scales with the size and complexity of an SoC and enables

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Presentation

Building Better IP with RTL Architect NoC IP Physical Exploration

Voted one of the “Top Ten Best Presentations” at SNUG Silicon Valley 2023, this presentation discusses the importance of NoCs and their impact on timing analysis and power consumption. It introduces a flow and methodology that utilizes RTL-based estimation of timing and power consumption using RTL Architect in conjunction with

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Presentation

Challenges Adopting Fault Injection to Support Safety Analysis in Complex SoCs

Learn about fault simulator and EDA tools requirements; Using FMEA to create fault injection campaign; Guidelines/lesson learned for simulating different fault types; Analysis and documentation.

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Solution Briefs

Solution Brief

Accelerate and Derisk RISC-V-based SoC Designs with Arteris

Connect RISC-V computing and accelerate subsystems with silicon-proven interconnect IP. Unify protocols such as AMBA across 100’s of re-used IP blocks cutting complexity and maximizing resource efficiency. Derisk project schedules with leading system IP and expert support.

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White Papers

White Paper

A Configurable Test Infrastructure using a Mixed-Language and Mixed-Level IP Integration IP-XACT Flow

This paper written with NXP describes an efficient integration flow for mixed-language and mixed-abstraction level IPs through IP-XACT flow automation.

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White Paper

A Design Flow for Critical Embedded Systems

In this paper by Airbus, Thales, STMicroelectronics, Arteris and other, learn how IP encapsulation/packaging and interoperability using IP-XACT enabled automation in a complex verification & validation flow for aeronautical systems.

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White Paper

A Power Consumption Estimation Approach for Embedded Software Design using Trace Analysis

This paper presents a lightweight and cost-effective approach to power estimation suitable for software developers. It relies on trace analysis and high-level modeling of architectures to perform quick and efficient power consumption estimations without losing accuracy.

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White Paper

A SystemC Extension for Enabling Tighter Integration of IP-XACT Platforms with Virtual Prototypes

This paper describes a configurable SystemC extension that simplifies the syntax for expressing register and bit field accesses and enables automation of virtual platform and hardware-software interface (HSI) development.

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White Paper

AMS System-Level Verification and Validation using UVM in SystemC and SystemC-AMS: Automotive Use Cases

This 12-page paper published in the peer-reviewed IEEE Design & Test journal explains how Universal Verification Methodology (UVM), initially developed for digital systems, can be extended to analog and mixed signal systems with the help if IP-XACT-based IP packaging and design flow automation.

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Videos

intro video

FlexGen Smart NoC IP from Arteris Revolutionizes Complex SoC Designs

FlexGen smart NoC IP enables automated NoC design with reduced manual effort, shorter iteration cycles, and expert-level quality of results. SoC design teams can realize faster time-to-market, optimized power plus performance, reduced wire length, and improved overall design economics with FlexGen.

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intro video

FlexNoC 5 Physically Aware Network-on-Chip IP

FlexNoC 5 physically aware network-on-chip IP incorporates physical constraint management across power, performance, and area (PPA). Get up to 5X faster physical convergence vs manual physical iterations and achieve PPA goals within schedule and budget constraints.

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intro video

Magillem Registers – Automate the Hardware/Software Interface for Fast Chip Design

Magillem Registers is a comprehensive register design and management technology that accurately automates the hardware/software interface (HSI) to quickly develop chips and chiplets ranging from IoT devices to complex AI datacenter multi-die SoCs.

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intro video

Ncore Cache Coherent Network-on-Chip IP from Arteris

Ncore cache coherent NoC IP is scalable, configurable, and ISO 26262 certified. With Ncore, teams can derisk their SoC designs and deliver on their vision in record time, saving upwards of 50 years of engineering effort per project compared to manually generated solutions.

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presentation

Accelerating Timing Closure for Networks-on-Chip (NoCs) using Physical Awareness

Learn how to accelerate timing closure for Networks-on-Chip (NoCs) using physical awareness. Discover a flow and methodology to optimize NoC development and avoid timing surprises.

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presentation

Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications

This presentation covered the challenges and solutions of data–transport architectures for AI and ML in the context of embedded vision architectures and the implementation aspects for NoCs for RISC–V–based SoCs.

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Webinars

Webinar

Revolutionizing SoC Performance with Network-on-Chip Technology

See how you can create NoCs with less wires, more bandwidth, smaller area with incredible efficiency, flexibility and scalability to achieve your SoC goals.

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Webinar

Three Perspectives on System Design Challenges

Explore the positive impact a single source of truth environment can have on the different teams involved in a SOC design and what it means to quickly enable consistent HSI output generation throughout an entire system design. Download the webinar and learn how to increase productivity and reduce risk to get to market faster with a proven, best-in-class approach that saves time and money.

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Case Studies

Datasheets

Infographics

Accelerating Timing Closure for Networks-on-Chip (NoCs) With Physical Awareness

A Single Source Unified Approach to CSR Register Development

Simplifying SoC Integration with Arteris

Podcasts

EE Times: Automating NoC Design Masters SoC Complexity

SemiWiki: How Arteris FlexGen Smart NoC IP Democratizes Advanced Chip Design

EE Journal: Managing the Massive Data Throughput: AI-Based Designs and The Value of NoC Tiling

Electronic Design: All About NoCs

SemiWiki: The Impact of Arteris on Automotive and Beyond with Frank Schirrmeister

SemiWiki: A Broad View of Design Architectures and the Role of the NoC with Arteris’ Michal Siwinski

Presentations

Architecting the Future of Deep Learning Presentation

Arm & Arteris AI and ISO 26262 Presentation

Arm TechCon: Implementing ISO 26262 Compliant AI Systems-on-Chip with Arm and Arteris

Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip (SoCs)

Building Better IP with RTL Architect NoC IP Physical Exploration

Challenges Adopting Fault Injection to Support Safety Analysis in Complex SoCs

Solution Briefs

White Papers

Making SoC Integration Simple – Achieve Higher Productivity and Quality

A Configurable Test Infrastructure using a Mixed-Language and Mixed-Level IP Integration IP-XACT Flow

A Design Flow for Critical Embedded Systems

A Power Consumption Estimation Approach for Embedded Software Design using Trace Analysis

A SystemC Extension for Enabling Tighter Integration of IP-XACT Platforms with Virtual Prototypes

AMS System-Level Verification and Validation using UVM in SystemC and SystemC-AMS: Automotive Use Cases

Videos

FlexGen Smart NoC IP from Arteris Revolutionizes Complex SoC Designs

FlexNoC 5 Physically Aware Network-on-Chip IP

Magillem Registers – Automate the Hardware/Software Interface for Fast Chip Design

Ncore Cache Coherent Network-on-Chip IP from Arteris

Accelerating Timing Closure for Networks-on-Chip (NoCs) using Physical Awareness

Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications

Webinars

Accelerate Time To Market With a First-Time Right Process

Arteris FlexNoC 5 – Industry’s First Physically Aware Network-on-Chip IP

How to Achieve Efficient Communication and Data Sharing in Multi-Core SoC Designs

Revolutionizing SoC Performance with Network-on-Chip Technology

Three Perspectives on System Design Challenges

Headquarters