Blog

Deploying commercial NoC IP and adopting advanced SoC integration tools empowers designers to better manage the growing number of IP blocks, ensure data consistency and meet the PPA requirements of today’s applications....

Multi-die architectures demand expert planning to ensure connectivity and performance. To address these challenges, structured assembly methodologies complemented by IP-XACT standards have become essential to provide a clear chip design fra...

The evolution from monolithic dies to multi-die systems using chiplets marks a pivotal advancement in semiconductor technology. It takes an ecosystem of partners to develop and refine multi-die systems effectively and Arteris is here to hel...

Enhancing SoC CPU performance doesn't have to break the bank with high-performing IP cores. Learn how cost-effective optimization of cache memory systems can maximize CPU output....

Optimized interconnect topology and system partitioning, give engineering teams an efficient strategy to achieve performance and cost targets....

Integrating cache memory into SoCs and IP blocks improves their performance and efficiency. This article highlights technologies and strategies to address challenges like cache coherency and power consumption....