Until recently, coherency was something normally associated with DRAM. But as chip designs become increasingly heterogeneous, incorporating more and different types of compute elements, it becomes harder to maintain coherency in that data without taking a significant hit on performance and power. The basic problem is that not all compute elements fetch and share data at the same speed, and systems need to account for that differential. Andy Nightingale, vice president of product management and marketing at Arteris, talks about the need to build cache coherency into designs in a way that minimizes any loss in performance, while also maintaining flexibility to allow different processing elements to be prioritized as needed.

To watch the discussion on Semiconductor Engineering, click here.