Resolve Critical SoC Design Challenges
Critical challenges in developing SoC designs include performance optimization, data access, and power efficiency. CodaCache® addresses these design challenges effectively through performance-optimized caching, efficient data access, and power optimization techniques.
CodaCache also tackles key challenges like system scalability, SoC integration, timing closure, layout congestion, and real-time processing by providing scalable cache solutions, seamless integration capabilities, and support for real-time processing.
Using FlexNoC/FlexWay and CodaCache IPs in the same SoC provides a unique value by delivering a high-performance, power-efficient, and scalable solution that meets the demanding requirements of modern SoC designs while reducing development time, risk, and cost.
CodaCache Last-Level Cache IP
Enhances performance and efficiency in SoC designs
Configurable Systems
CodaCache's configurability fine-tunes settings for optimal performance, unlocking the full potential of the cache in specific scenarios.
Faster Performance
Facilitates fast and convenient access to frequently accessed data, eliminating the need to access the main memory, resulting in enhanced performance.
Seamless Integration
AXI support enables efficient communication between components, easy integration into existing SoC designs and accelerating development processes.
CodaCache Key Features
- Flexible physical organization
- Associativity
- Per way configurable scratchpad memory
- Way partitioning
- Performance monitors
- Performance models
- Functional safety
- Graphical user interface (GUI)
- Assisted coherency management
via hardware cache flush
Efficient Transport of Data Through the SoC
Companion for Arteris FlexNoC® and FlexWay®
- Ideal for NoC applications with data re-use
- Improves overall SoC latency and power
Learn about FlexNoC
CodaCache Product Benefits
Higher Frequencies, Lower Latencies
Enhances system and IP performance through optimized caching and efficient data access
Lower Power Consumption
Fewer off-chip main memory accesses resulting in lower power consumption
Smaller Die Area
Through its highly distributed architecture and configurable cache partitions
Easy Configuration
Through an intuitive and user-friendly interface
Automated Verification
Saving hundreds of hours of work over manual verification generation
Shorter Schedules
Shorter Schedules
Read more about why we are unique on our NoC Technology page.
CodaCache Product Options
Cache Line Options
- Up to 128 Bytes
- Up to 256 Bytes
- Up to 512 Bytes
The Arteris CodaCache reduces memory bottlenecks and saves power by allowing system-on-chip to employ a highly configurable last-level cache rather than solely communicating with off-chip memory. Designers will be attracted to the variety of use cases that CodaCache IP supports, including dedicated, shared, and distributed partitioning, as well as its use as on-chip scratchpad storage.
The Linley Group
Mike Demler, Senior Analyst, The Linley Group
Arteris NoC technology enables wide on-chip bandwidth with fewer wires and lower latency than traditional bus and crossbar fabrics. This multiuse deal is expected to help us deliver these benefits more quickly to engineering teams throughout Freescale.
Freescale
Fares Bagh, Vice President of R&D, Freescale
