Resolve Critical SoC Design Challenges
Critical challenges in developing SoC designs include performance optimization, data access, and power efficiency. CodaCache® addresses these design challenges effectively through performance-optimized caching, efficient data access, and power optimization techniques.
CodaCache also tackles key challenges like system scalability, SoC integration, timing closure, layout congestion, and real-time processing by providing scalable cache solutions, seamless integration capabilities, and support for real-time processing.
Using FlexNoC/FlexWay and CodaCache IPs in the same SoC provides a unique value by delivering a high-performance, power-efficient, and scalable solution that meets the demanding requirements of modern SoC designs while reducing development time, risk, and cost.
CodaCache Last-Level Cache IP
Enhances performance and efficiency in SoC designs
CodaCache's configurability fine-tunes settings for optimal performance, unlocking the full potential of the cache in specific scenarios.
Facilitates fast and convenient access to frequently accessed data, eliminating the need to access the main memory, resulting in enhanced performance.
AXI support enables efficient communication between components, easy integration into existing SoC designs and accelerating development processes.
CodaCache Key Features
- Flexible physical organization
- Configurable proxy cache
- Configurable snoop filters
- Per way configurable scratchpad memory
- Way partitioning
- Performance monitors
- Performance models
- Functional safety
- Graphical user interface (GUI)
- Assisted coherency management
via hardware cache flush
CodaCache Product Benefits
Higher Frequencies, Lower Latencies
Enhances system and IP performance through optimized caching and efficient data access
Lower Power Consumption
Fewer off-chip main memory accesses resulting in lower power consumption
Smaller Die Area
Through its highly distributed architecture and configurable cache partitions
Through an intuitive and user-friendly interface
Saving hundreds of hours of work over manual verification generation
Read more about why we are unique on our NoC Technology page.
The Arteris CodaCache reduces memory bottlenecks and saves power by allowing system-on-chip to employ a highly configurable last-level cache rather than solely communicating with off-chip memory. Designers will be attracted to the variety of use cases that CodaCache IP supports, including dedicated, shared, and distributed partitioning, as well as its use as on-chip scratchpad storage.
The Linley GroupMike Demler, Senior Analyst, The Linley Group
Arteris NoC technology enables wide on-chip bandwidth with fewer wires and lower latency than traditional bus and crossbar fabrics. This multiuse deal is expected to help us deliver these benefits more quickly to engineering teams throughout Freescale.
FreescaleFares Bagh, Vice President of R&D, Freescale