Arm and Arteris: Connecting the future of computing
Simplifying connectivity for mobility, communications, and intelligent IoT with plug-and-play network-on-chip connectivity, scalable from irregular to mesh architectures.
Overview
Accelerating innovation for next-gen chips
Arm technology centers on power-efficient computing, and Arm compute platforms are recognized as the most power-efficient available, pushing the thresholds of performance for the next generation of intelligent, AI-capable, visually immersive, and more autonomous experiences everywhere.
Arteris plays a crucial role in the Arm ecosystem, providing the system IP, software tools and expertise needed to bring sophisticated Arm-based designs to life. Arteris is strategically positioned to connect semiconductor IP building blocks in Arm-based designs, particularly in automotive mobility, mobile applications, and IoT, addressing the escalating demand for more intelligent, specialized devices. Arteris complements the Arm architecture by offering advanced network-on-chip (NoC) and system-on-chip (SoCs) integration automation solutions that facilitate the seamless integration of Arm cores with other IP blocks. Together, we optimize the design and functionality of complex SoCs and chiplet systems.
Arteris designed configurable and scalable NoC solutions to streamline the integration process, allowing designers to focus on innovation and differentiation without being hindered by the underlying chip architecture complexity. With about two decades of collaboration, Arm and Arteris help ensure that Arm-based designs are feasible and optimized for performance and energy efficiency. The collaboration helps accelerate the design-to-market process and minimize project risks, which supports customer success and drives the next wave of innovation in the semiconductor industry.
Advantages
Arteris simplifies SoC design and integration
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Pre-validation
Arteris network-on-chip (NoC) technology and Arm Automotive Enhanced (AE) Armv9 products have been pre-validated in emulation as part of our collaboration to ensure interoperability.
Expertise in connectivity
With over 20 years of experience, Arteris simplifies the complexities of inter-chip and intra-chip connectivity, so designers can focus on core innovation, while accelerating design to market.
Scalability
Create highly scalable ring, mesh, and heterogenous topologies and edit generated topologies (in contrast to black box compiler and mesh-only approaches) to optimize each network router.
Arteris is pleased to collaborate with Arm to speed up automotive electronics innovation with an emulation-based validation system for Armv9 and CHI-E-based designs for autonomous driving, advanced driver-assistance systems (ADAS), cockpit and infotainment, vision, radar and lidar, body and chassis control, zonal controllers, and other automotive applications.
Arteris aligned its roadmap with Arm to help designers accelerate time to market with an optimized and pre-validated high-bandwidth, low-latency Arteris Ncore cache coherent interconnect IP for the Arm Automotive Enhanced (AE) compute portfolio. Our partnership helps customers achieve high-performance, power-efficient SoCs for safety-critical tasks, while reducing project schedules and costs. Mutual customers benefit from an increased choice of safe, integrated, and optimized automotive solutions to speed time to market through seamless integration and optimized flows. We also help ensure high-quality results, enabling ISO 26262 systems with the highest automotive safety integrity levels (ASIL).
Design for next-gen demands with Ncore Cache Coherent NoC IP
Ncore is the only scalable, highly configurable, ISO 26262 certified cache coherent NoC for modern SoC designs.
- Any processor
- Multiple protocols
- Flexible configuration
Maximize engineering productivity and accelerate time-to-market with Ncore. Our white paper shows how you could save 50+ person years over a DIY project.
Products
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Products for Arm designs
Customers
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- EE Journal: Managing the Massive Data Throughput: AI-Based Designs and The Value of NoC Tiling
- EE Journal: The Network-on-Chip Pioneer: How Arteris Enabling SoC Developers to Create Physically Valid NoCs Faster
- Electronic Design: All About NoCs
- SemiWiki: The Impact of Arteris on Automotive and Beyond with Frank Schirrmeister
- SemiWiki: A Broad View of Design Architectures and the Role of the NoC with Arteris’ Michal Siwinski
- SemiWiki: The Impact of Using a Physically Aware NoC with Charlie Janac
- Arm & Arteris AI and ISO 26262 Presentation
- Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip (SoCs)
- Building Better IP with RTL Architect NoC IP Physical Exploration
- Efficient Scaling of AI Accelerators Using NoC Tiling
- FMEDA Automation for Scalability and Reuse in Complex Systems on Chips (SoCs)
- Is the Missing Safety Ingredient in Automotive AI Traceability?
- Lessons Learned Integrating AI/ML Accelerators into Complex ISO 26262 Compliant Systems-on-Chip
- Safety Considerations for Network-on-Chip (NoC) Development
- The Role of Networks-on-Chips Enabling AI/ML Silicon and Systems
- Tiled Approach to System Scaling
- Magillem Registers – Automate the Hardware/Software Interface for Fast Chip Design
- Accelerating Timing Closure for Networks-on-Chip (NoCs) using Physical Awareness
- FlexGen Product Tour
- Cache Coherency in Heterogeneous Systems
- Integration Challenges for RISC-V Designs
- Promises and Pitfalls of SoC Restructuring
- Scaling Performance in AI Systems
- Accelerate Time To Market With a First-Time Right Process
- Arteris FlexNoC 5 – Industry’s First Physically Aware Network-on-Chip IP
- How to Achieve Efficient Communication and Data Sharing in Multi-Core SoC Designs
- Revolutionizing SoC Performance with Network-on-Chip Technology
- Three Perspectives on System Design Challenges
- Making SoC Integration Simple – Achieve Higher Productivity and Quality
- A Configurable Test Infrastructure using a Mixed-Language and Mixed-Level IP Integration IP-XACT Flow
- A Design Flow for Critical Embedded Systems
- A Power Consumption Estimation Approach for Embedded Software Design using Trace Analysis
- AMS System-Level Verification and Validation using UVM in SystemC and SystemC-AMS: Automotive Use Cases
- Building a Portable Stimulus Flow Based on Magillem IP-XACT Packaging
- CodaCache: Helping to Break the Memory Wall
- Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product
- HW / SW Interface Generation Flow Based on Abstract Models of System Applications and Hardware Architectures
- Power Dissipation of the Network-on-Chip in a System-on-Chip for MPEG-4 Video Encoding
- Re-Architecting SoCs for the AI Era
- Scalability – A Looming Problem in Safety Analysis
- Security in Artificial Intelligence
- Using Machine Learning for Characterizations of NoC Components
- Using Virtual Prototypes to Improve the Traceability of Critical Embedded Systems Flow
- Boost SoC Efficiency and Speed with FlexGen Smart NoC IP Automation White Paper
- Making Cache Coherent SoC Design Easier with Ncore
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