Magillem 5 Registers
Faster Time to Market With an Error-Free System Memory Map
Enabling Effective Hardware/Software Interface Development for Schedule Acceleration
Magillem® 5 Registers offers a single source of truth methodology based on the IP-XACT standard, which not only targets the traditional need to manage registers, but also addresses today’s HW/SW integration challenges for large-scale SoCs.
Magillem 5 Registers enables quick and scalable automated implementation, cutting the time to market for the Hardware/Software Interface (HSI) generation in half.
Straightforward Register Intent Capture
Magillem 5 Registers translates the specification of registers into executable design code by automatically importing the register descriptions from different sources and formats into IP-XACT.
- Automatically checks the accuracy of the information (overlaps, configurability, reserved empty spaces, …).
- Enables close collaboration between HW, SW, and tech doc teams through a single source of truth methodology for consistently generated data.
- Comprehensive HSI automation ensures better quality design and faster productivity.
Automatically Generate Consistent Data
Generated data is always consistent and complete, which allows the verification team to always have an up-to-date generated register model to work from.
Magillem Registers 5 supports customizable generators in addition to the automatic generation of standard output formats:
- RTL register bank generation
- Software headers generation
- UVM RAL generation
- Arm CMSIS-SVD file generation
- Docx and HTML documentation generation
Error-Free System Map Generation
Synchronizing connectivity and memory map information with full integration of Magillem 5 Registers and Magillem 5 Connectivity:
- Calculate and display the system map from the selected initiator.
- Confirm that memory regions defined in the memory map can be reached (presence of a physical path).
- Check that all the SW visible elements (registers or memory regions) in connected targets are present in the memory map.
Magillem 5 Registers Key Features
- Single Database: Import and capture memory map information into a single database (IP-XACT)
- Parameterization: including configurable properties, custom specific access types and register modes
- Comprehensive Checkers: Catch errors early in the process with built-in and custom checkers
- Standard Formats Support: Output standard formats for HW design and verification, embedded SW, and documentation
- Custom Templates: Advanced generation capability with support for custom template-based generators
- Merge/Flatten IP Memory: Enable easy update/manipulation/creation of new global memory map for a sub-system or SoC
- Tool Integration: Tight link with the connectivity tool to generate a system address map when both tools are combined
Magillem 5 Registers Product Benefits
Quick & Easy Adoption
Intuitive yet powerful GUI cuts learn curve and eases adoption
Seamless Integration
Define and customize importer/exporter/register property definitions for seamless integration
Scalable & Expansive
Use on up to 100Ks registers plus large-scale SoC memory maps
Automated & Efficient
Reduce tedious and error-prone tasks with fully-automated flow and shorten the overall process
Accurate & Consistent
Count on a single source of truth with HW, SW and documentation all in sync to ensure accuracy and cross-team consistency
Quality Assurance
Catch errors at the data entry stage with the memory map information before running any simulation
Productivity Booster
Accelerate the schedule with a correct-by-construction SW interface
Read more about why we are unique on our NoC Technology page.
Product Options
Seamlessly Integrated Extensions to the Base Feature Set
Architectural Option: System Map Import and Generation
- Automatically create the entire IP-XACT platform from the xls file input describing the system map
- Automatic configuration of the bridges according to the system map reference
- Enable keeping both software and hardware ends synchronized
Safety Option: Functional Safety Reg Bank
- Single/Double Error Detection: register byte parity bit and register duplication
- SW and HW Interface Protection: AMBA check types
- Error reporting: error output bits and protocol error signaling
- Ensure support of safety requirements for automotive industry
We automatically generated 2 Million lines of register header files for just one chip! And we automated much of our Linux device tree and low-level firmware development.
Texas Instruments
Software Manager, Texas Instruments
- Infographic: Simplifying SoC Integration
- Webinar: Accelerate Time To Market With an IP-XACT-Based First-Time Right SoC Integration Process
- White Paper: Making SoC Integration Simple
- Blogs
- Accelerating Time to Market with an IP-XACT-based First-Time-Right SoC Integration Process | ChipEstimate
- Navigating the Hardware-Software Interface in Chip Design | Electronic Design
- SoC Integration And Data Transport Architecture Requirements Surge In 2023 | Semiconductor Engineering