Magillem Registers
Faster Time to Market With an Error-Free System Memory Map
Enabling Effective Hardware/Software Interface Development for Schedule Acceleration
Magillem® Registers offers a single source of truth methodology, which not only targets the traditional need to manage registers, but also addresses today’s HW/SW integration challenges for large-scale SoCs.
Magillem Registers enables quick and scalable automated implementation, cutting the time to market for the Hardware/Software Interface (HSI) generation in half.
Straightforward Register Intent Capture
Magillem Registers translates the specification of registers into executable design code by automatically importing the register descriptions from different sources and formats.
- Automatically checks the accuracy of the information (overlaps, configurability, reserved empty spaces, …).
- Enables close collaboration between HW, SW, and tech doc teams through a single source of truth methodology for consistently generated data.
- Comprehensive HSI automation ensures better quality design and faster productivity.
Automatically Generate Consistent Data
It is a true cross-compiler with over 1,000 functional, behavioral, syntactic, and semantic error checks. It supports various formats and generates multiple outputs simultaneously.
Generated data is always consistent and complete, which allows the verification team to always have an up-to-date generated register model to work from.
Error-Free System Map Generation
Synchronizing connectivity and memory map information with full integration of Magillem Registers and Magillem Connectivity:
- Calculate and display the system map from the selected initiator.
- Confirm that memory regions defined in the memory map can be reached (presence of a physical path).
- Check that all the SW visible elements (registers or memory regions) in connected targets are present in the memory map.
Magillem Registers Key Features
- Single Database: Import and capture memory map information into a single database for generating RTL, digital verification, firmware, and documentation
- Various input formats: CSRSpec language, SystemRDL, IP-XACT 2009/2014/2022, spreadsheets…
- Extensive error/syntax checking: with over 1,000 error checks
- Alternative UVM backdoor methodology: for high performance on large designs
- Advanced features: Registers broadcast/alias, virtual registers, wide memories and atomic access support
- Tool Integration: Tight link with the connectivity tool to generate a system address map when both tools are combined
Explore additional features of Magillem Registers, download the datasheet.
Magillem Registers Product Benefits
Easy Specification Adjustment
Very fast iteration with updated information across design teams ensuring data consistency
Agile Design Process
Ensure best practices and early engagement of the entire design team
Scalable & Expansive
Compile over 5 million registers plus use on large-scale SoC memory maps
Automated & Efficient
Reduce tedious and error-prone tasks with fully-automated flow and shorten the overall process
Accurate & Consistent
Count on a single source of truth with HW, SW and documentation all in sync to ensure accuracy and cross-team consistency
Quality Assurance
Catch errors at the data entry stage with the memory map information before running any simulation
Productivity Booster
Accelerate the schedule with a correct-by-construction SW interface
Read more about why we are unique on our NoC Technology page.
- Infographic: Simplifying SoC Integration
- Webinar: Accelerate Time To Market With an IP-XACT-Based First-Time Right SoC Integration Process
- White Paper: Making SoC Integration Simple
- Press Releases
- Blogs
- Accelerating Time to Market with an IP-XACT-based First-Time-Right SoC Integration Process | ChipEstimate
- Navigating the Hardware-Software Interface in Chip Design | Electronic Design
- SoC Integration And Data Transport Architecture Requirements Surge In 2023 | Semiconductor Engineering